From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755846AbcAMSWF (ORCPT ); Wed, 13 Jan 2016 13:22:05 -0500 Received: from mga03.intel.com ([134.134.136.65]:40074 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750866AbcAMSWB (ORCPT ); Wed, 13 Jan 2016 13:22:01 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,290,1449561600"; d="scan'208";a="889838043" Date: Wed, 13 Jan 2016 10:21:38 -0800 From: Jacob Pan To: Borislav Petkov Cc: Thomas Gleixner , LKML , Linux PM , Rafael Wysocki , "H. Peter Anvin" , Ingo Molnar , X86 Kernel , Srinivas Pandruvada , Peter Zijlstra , jacob.jun.pan@linux.intel.com Subject: Re: [PATCH v2 2/2] powercap/rapl: reduce ipi calls Message-ID: <20160113102138.4e34e890@yairi> In-Reply-To: <20160113180412.GN12897@pd.tnic> References: <1452647483-14244-1-git-send-email-jacob.jun.pan@linux.intel.com> <1452647483-14244-3-git-send-email-jacob.jun.pan@linux.intel.com> <20160113082113.3314fa92@icelake> <20160113163610.GH12897@pd.tnic> <20160113095124.186ff487@yairi> <20160113180412.GN12897@pd.tnic> Organization: OTC X-Mailer: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 13 Jan 2016 19:04:12 +0100 Borislav Petkov wrote: > > Then i was suggested to add a rmw msr api for the common good :), I > > think it is a good idea since such operation is not limited to RAPL > > driver. > > Others are...? nothing for the _safe version right now. Quick scan through the code I see the non safe version has a couple can be converted to rmw. e.g. static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) { ... rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); if (newstate == DC_DISABLE) { pr_debug("CPU#%d disabling modulation\n", cpu); wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); } else { pr_debug("CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10)); /* bits 63 - 5 : reserved * bit 4 : enable/disable * bits 3-1 : duty cycle * bit 0 : reserved */ l = (l & ~14); l = l | (1<<4) | ((newstate & 0x7)<<1); wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); } static int sfi_cpufreq_target(struct cpufreq_policy *policy, unsigned int index) { ... rdmsr_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, &lo, &hi); lo = (lo & ~INTEL_PERF_CTL_MASK) | ((u32) sfi_cpufreq_array[next_perf_state].ctrl_val & INTEL_PERF_CTL_MASK); wrmsr_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, lo, hi);