Re: [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config

Thierry Reding
2016-01-13T14:00:24Z

[-- Attachment #1: Type: text/plain, Size: 1029 bytes --]

On Fri, Jan 08, 2016 at 01:45:13PM -0500, Rhyland Klein wrote:
> From: Mark Kuo <mkuo@nvidia.com>
>
> Fix PLLE spread spectrum configuration so it aligns with downstream
> kernel.
>
> Signed-off-by: Mark Kuo <mkuo@nvidia.com>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
> drivers/clk/tegra/clk-pll.c | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)

Can we have a better description for this. Merely saying that this is
meant to align things with downstream isn't really helpful for anyone
who doesn't have the downstream kernel to check against.

I also see some potential for splitting this up into several logical
changes, since for example it seems to fix a typo (?) where some bits
were being set that should really be cleared, and in other hunks it
splits up the SS coefficients by SoC generation. Splitting it up into
logical changes might make it easier to write accurate commit
descriptions rather than this kind of blanket commit message.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]