From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752016AbcAMPbh (ORCPT ); Wed, 13 Jan 2016 10:31:37 -0500 Received: from mail-cys01nam02on0082.outbound.protection.outlook.com ([104.47.37.82]:38016 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751705AbcAMPbe (ORCPT ); Wed, 13 Jan 2016 10:31:34 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Date: Wed, 13 Jan 2016 07:31:13 -0800 From: =?utf-8?B?U8O2cmVu?= Brinkmann To: Subbaraya Sundeep Bhatta CC: , , , , , , Subbaraya Sundeep Bhatta Subject: Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY. Message-ID: <20160113153113.GL6491@xsjsorenbubuntu> References: <1452694404-1253-1-git-send-email-sbhatta@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1452694404-1253-1-git-send-email-sbhatta@xilinx.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22060.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(199003)(24454002)(377424004)(189002)(77096005)(50466002)(23676002)(5008740100001)(586003)(81156007)(110136002)(11100500001)(4326007)(19580405001)(6806005)(1220700001)(2950100001)(5001960100002)(92566002)(33656002)(189998001)(4001350100001)(63266004)(19580395003)(107886002)(36386004)(57986006)(85182001)(85202003)(47776003)(106466001)(4001450100002)(87936001)(33716001)(1096002)(1076002)(76176999)(76506005)(83506001)(50986999)(54356999)(4001430100002)(86362001)(2906002)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT245;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;A:1;MX:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: ba0abb1c-34f2-41d2-8463-08d31c2e9cc2 X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT245;UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: <3d38bc584ae24176a24e2d4216314f7b@SN1NAM02HT245.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(8121501046)(13015025)(5005006)(13018025)(520078)(13017025)(10201501046)(3002001);SRVR:SN1NAM02HT245;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT245; X-Forefront-PRVS: 08200063E9 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2016 15:31:31.0782 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT245 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2016-01-13 at 07:43PM +0530, Subbaraya Sundeep Bhatta wrote: > This patch adds the document describing dt bindings for ZynqMP > PHY. ZynqMP SOC has a High Speed Processing System Gigabit > Transceiver which provides PHY capabilties to USB, SATA, > PCIE, Display Port and Ehernet SGMII controllers. > > Signed-off-by: Subbaraya Sundeep Bhatta I missed the v2 hence again. > --- > v2: > modified to use phy cells as 2. > > .../devicetree/bindings/phy/phy-zynqmp.txt | 103 +++++++++++++++++++++ > 1 file changed, 103 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt > new file mode 100644 > index 0000000..975cf21 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt > @@ -0,0 +1,103 @@ > +Xilinx ZynqMP PHY binding > + > +This binding describes a ZynqMP PHY device that is used to control ZynqMP > +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes > +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers. > + > +Required properties (controller (parent) node): > +- compatible : Should be "xlnx,zynqmp-psgtr" > + > +- reg : Address and length of register sets for each device in > + "reg-names" > +- reg-names : The names of the register addresses corresponding to the > + registers filled in "reg": > + - serdes: SERDES block register set > + - siou: SIOU block register set > + - lpd: Low power domain peripherals reset control > + - fpd: Full power domain peripherals reset control The reset registers should not be directly modified by Linux. Any access to resets is likely requiring a reset controller that uses platform FW to modify the resets. > + > +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX > + termination resistance can be out of spec due to a > + bug in the calibration logic. This issue will be fixed > + in silicon in future versions. The silicon version is run-time detectable. There should be a way to get away without this property. Sören