From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756948AbcANWyW (ORCPT ); Thu, 14 Jan 2016 17:54:22 -0500 Received: from mail.skyhub.de ([78.46.96.112]:43619 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754568AbcANWyT (ORCPT ); Thu, 14 Jan 2016 17:54:19 -0500 Date: Thu, 14 Jan 2016 23:53:59 +0100 From: Borislav Petkov To: Aravind Gopalakrishnan Cc: tony.luck@intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank Message-ID: <20160114225359.GL19941@pd.tnic> References: <1452809140-3328-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <1452809140-3328-4-git-send-email-Aravind.Gopalakrishnan@amd.com> <20160114223739.GJ19941@pd.tnic> <569825B6.6020507@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <569825B6.6020507@amd.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 14, 2016 at 04:48:22PM -0600, Aravind Gopalakrishnan wrote: > True. But that BlkPtr logic also will undergo changes as it's interpretation > for future processors is different. But there still must be a bit there which says "this register is valid", like MCi_MISC[63]. And so I'd very much prefer checking a bit (or bits) instead of relying on defines. > We are guaranteed to have all the MISC registers (all 5 of them) going > forward. Guarantees are worth nothing. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.