From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753569AbcAOCpj (ORCPT ); Thu, 14 Jan 2016 21:45:39 -0500 Received: from mail-pa0-f67.google.com ([209.85.220.67]:35658 "EHLO mail-pa0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751957AbcAOCpg (ORCPT ); Thu, 14 Jan 2016 21:45:36 -0500 Date: Thu, 14 Jan 2016 18:45:35 -0800 From: Nicolin Chen To: Caleb Crome Cc: Timur Tabi , Xiubo Li , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "alsa-devel@alsa-project.org" Subject: Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst settings device tree options Message-ID: <20160115024534.GB29132@Asurada-Nvidia> References: <1452788982-11583-1-git-send-email-caleb@crome.org> <20160114201858.GA17567@Asurada-Nvidia> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 14, 2016 at 01:26:24PM -0800, Caleb Crome wrote: > As for optimal settings, I finally came to a setting of 4 for depth & > maxburst, which will result in more DMA requests, but it's the only > way that works at 48kHz for me. The default settings is 13 (15 - 2) > for the ones of the 15 item fifo, which is a pretty dramatic > difference. I just don't know if other chips will behave badly in > that case. What's your final configuration for TFWM0 bits, 4?