From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758259AbcATI5t (ORCPT ); Wed, 20 Jan 2016 03:57:49 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:6337 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751144AbcATI5m (ORCPT ); Wed, 20 Jan 2016 03:57:42 -0500 Date: Wed, 20 Jan 2016 16:53:19 +0800 From: Jisheng Zhang To: Thomas Petazzoni CC: , , , , , , , , , , , Subject: Re: [PATCH 3/4] net: mvneta: mmc: get optional axi clk Message-ID: <20160120165319.5ee8589a@xhacker> In-Reply-To: <20160120095132.29896293@free-electrons.com> References: <1453277183-5412-1-git-send-email-jszhang@marvell.com> <1453277183-5412-4-git-send-email-jszhang@marvell.com> <20160120095132.29896293@free-electrons.com> X-Mailer: Claws Mail 3.13.1 (GTK+ 2.24.29; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-01-20_03:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310008 definitions=main-1601200161 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 20 Jan 2016 09:51:32 +0100 Thomas Petazzoni wrote: > Dear Jisheng Zhang, > > On Wed, 20 Jan 2016 16:06:22 +0800, Jisheng Zhang wrote: > > Some platforms may provide more than one clk for the mvneta IP, for > > example Marvell BG4CT provides "core" clk for the mac core, and > > "axi" clk for the AXI bus logic. Obviously this "axi" clk also need to > > be enabled. This patch adds this optional "axi" clk support. > > > > Signed-off-by: Jisheng Zhang > > Typo in the title, you have "mmc: ", while this patch is not related to > MMC, unless I'm missing something and MMC means something else in this > context. oops, thanks for pointing out this. > > > clk_prepare_enable(pp->clk); > > > > + pp->clk_axi = devm_clk_get(&pdev->dev, "axi"); > > + if (!IS_ERR(pp->clk_axi)) > > + clk_prepare_enable(pp->clk_axi); > > + > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > pp->base = devm_ioremap_resource(&pdev->dev, res); > > if (IS_ERR(pp->base)) { > > @@ -3727,6 +3733,7 @@ err_free_ports: > > free_percpu(pp->ports); > > err_clk: > > clk_disable_unprepare(pp->clk); > > + clk_disable_unprepare(pp->clk_axi); > > For the error paths and cleanup steps, I very much prefer when things > are done in the opposite order of the allocation/creation steps. So can > you clk_disable_unprepare() the AXI clock before the core clock ? Both are fine. But I agree with your prefer. Will cook a v2 soon Thanks for reviewing. > > > err_put_phy_node: > > of_node_put(phy_node); > > err_free_irq: > > @@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev) > > > > unregister_netdev(dev); > > clk_disable_unprepare(pp->clk); > > + clk_disable_unprepare(pp->clk_axi); > > Ditto. > > Thanks! > > Thomas