From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934366AbcATJqu (ORCPT ); Wed, 20 Jan 2016 04:46:50 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:2579 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932998AbcATJqo (ORCPT ); Wed, 20 Jan 2016 04:46:44 -0500 Date: Wed, 20 Jan 2016 17:42:23 +0800 From: Jisheng Zhang To: Sebastian Hesselbarth CC: , , , , , , , , , , , Subject: Re: [PATCH 3/4] net: mvneta: mmc: get optional axi clk Message-ID: <20160120174223.53ccc36b@xhacker> In-Reply-To: <1525e5fba70.2764.107cef0f820c2f5d7b7f41463071c310@gmail.com> References: <1453277183-5412-1-git-send-email-jszhang@marvell.com> <1453277183-5412-4-git-send-email-jszhang@marvell.com> <1525e5fba70.2764.107cef0f820c2f5d7b7f41463071c310@gmail.com> X-Mailer: Claws Mail 3.13.1 (GTK+ 2.24.29; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-01-20_04:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310008 definitions=main-1601200172 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 20 Jan 2016 10:31:18 +0100 Sebastian Hesselbarth wrote: > On January 20, 2016 9:15:22 AM Jisheng Zhang wrote: > > > Some platforms may provide more than one clk for the mvneta IP, for > > example Marvell BG4CT provides "core" clk for the mac core, and > > "axi" clk for the AXI bus logic. Obviously this "axi" clk also need to > > be enabled. This patch adds this optional "axi" clk support. > > Jisheng, > > although I do not expect mvneta to appear on a non-AXI bus > anytime soon, how about naming the clock "bus" instead? Good question. IIRC, this IP expects AXI bus, but I'll check with HW people. Thanks a lot, Jisheng > > If you know the clock is only required for bus master DMA but > not for register access, "dma" would be an even better name. > > Sebastian > > > > Signed-off-by: Jisheng Zhang > > --- > > drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/net/ethernet/marvell/mvneta.c > > b/drivers/net/ethernet/marvell/mvneta.c > > index aca0a73..6bb709a 100644 > > --- a/drivers/net/ethernet/marvell/mvneta.c > > +++ b/drivers/net/ethernet/marvell/mvneta.c > > @@ -373,6 +373,8 @@ struct mvneta_port { > > > > /* Core clock */ > > struct clk *clk; > > + /* AXI clock */ > > + struct clk *clk_axi; > > u8 mcast_count[256]; > > u16 tx_ring_size; > > u16 rx_ring_size; > > @@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev) > > > > clk_prepare_enable(pp->clk); > > > > + pp->clk_axi = devm_clk_get(&pdev->dev, "axi"); > > + if (!IS_ERR(pp->clk_axi)) > > + clk_prepare_enable(pp->clk_axi); > > + > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > pp->base = devm_ioremap_resource(&pdev->dev, res); > > if (IS_ERR(pp->base)) { > > @@ -3727,6 +3733,7 @@ err_free_ports: > > free_percpu(pp->ports); > > err_clk: > > clk_disable_unprepare(pp->clk); > > + clk_disable_unprepare(pp->clk_axi); > > err_put_phy_node: > > of_node_put(phy_node); > > err_free_irq: > > @@ -3744,6 +3751,7 @@ static int mvneta_remove(struct platform_device *pdev) > > > > unregister_netdev(dev); > > clk_disable_unprepare(pp->clk); > > + clk_disable_unprepare(pp->clk_axi); > > free_percpu(pp->ports); > > free_percpu(pp->stats); > > irq_dispose_mapping(dev->irq); > > -- > > 2.7.0.rc3 > > > >