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Date: Thu, 21 Jan 2016 16:10:40 +0100
From: Peter Zijlstra <peterz@infradead.org>
To: Huang Rui <ray.huang@amd.com>
Cc: Borislav Petkov <bp@suse.de>, Ingo Molnar <mingo@kernel.org>,
        Andy Lutomirski <luto@amacapital.net>,
        Thomas Gleixner <tglx@linutronix.de>, Robert Richter <rric@kernel.org>,
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        =?utf-8?B?RnLvv71k77+9cmlj?= Weisbecker <fweisbec@gmail.com>,
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        Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
        Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>,
        Borislav Petkov <bp@alien8.de>, Fengguang Wu <fengguang.wu@intel.com>,
        Aaron Lu <aaron.lu@intel.com>
Subject: Re: [PATCH v2 5/5] perf/x86/amd/power: Add AMD accumulated power
 reporting mechanism
Message-ID: <20160121151040.GO6356@twins.programming.kicks-ass.net>
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On Thu, Jan 21, 2016 at 10:42:35PM +0800, Huang Rui wrote:
> > > @@ -164,14 +171,14 @@ static int pmu_event_add(struct perf_event *event, int mode)
> > >  	struct hw_perf_event *hwc = &event->hw;
> > >  	unsigned long flags;
> > >  
> > > -	spin_lock_irqsave(&pmu->lock, flags);
> > > +	raw_spin_lock_irqsave(&pmu->lock, flags);
> > >  
> > >  	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
> > >  
> > >  	if (mode & PERF_EF_START)
> > >  		__pmu_event_start(pmu, event);
> > >  
> > > -	spin_unlock_irqrestore(&pmu->lock, flags);
> > > +	raw_spin_unlock_irqrestore(&pmu->lock, flags);
> > >  
> > >  	return 0;
> > >  }
> > 
> > So for these 4 {start,stop,add,del} you can drop the irqsave/irqrestore
> > thing as its guaranteed that IRQs will be disabled.
> > 
> 
> OK, I will remove the lock.

No, the lock seems needed, as the list is global. Just the
irqsave/irqrestore part is superfluous.

> > > +	cpumask_clear(pmu->mask);
> > > +	cpumask_clear(pmu->tmp_mask);
> > >  
> > >  	for (i = 0; i < cores_per_cu; i++)
> > > +		cpumask_set_cpu(i, pmu->mask);
> > >  
> > > +	cpumask_shift_left(pmu->mask, pmu->mask, cu * cores_per_cu);
> > 
> > Couldn't you simply use topology_sibling_cpumask(cpu) instead?
> > 
> 
> Looks like we couldn't. That's because cores number per cu (compute
> unit) is got by CPUID 0x8000001e EBX. That relies on the CPU hardware.

Borislav? I thought the AMD compute unit stuff was modeled as the SMT
topology.