From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754613AbcAVUbo (ORCPT ); Fri, 22 Jan 2016 15:31:44 -0500 Received: from down.free-electrons.com ([37.187.137.238]:55821 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752631AbcAVUbl (ORCPT ); Fri, 22 Jan 2016 15:31:41 -0500 Date: Fri, 22 Jan 2016 21:31:38 +0100 From: Maxime Ripard To: Chen-Yu Tsai Cc: Ulf Hansson , Hans de Goede , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Message-ID: <20160122203138.GB3682@lukather> References: <1453354002-28366-1-git-send-email-wens@csie.org> <1453354002-28366-9-git-send-email-wens@csie.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="XOIedfhf+7KOe/yw" Content-Disposition: inline In-Reply-To: <1453354002-28366-9-git-send-email-wens@csie.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --XOIedfhf+7KOe/yw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi,=20 On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote: > mmc2 and mmc3 are available on the same pins, with different mux values. > However, only mmc3 supports 8 bit DDR transfer modes. >=20 > Since preference for mmc3 over mmc2 is due to DDR transfer modes, just > set the drive strength to 40mA, which is needed for DDR. >=20 > This pinmux setting also includes the hardware reset pin for emmc. >=20 > Signed-off-by: Chen-Yu Tsai > --- > arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) >=20 > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a= 31.dtsi > index b6ad7850fac6..1867af24ff52 100644 > --- a/arch/arm/boot/dts/sun6i-a31.dtsi > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi > @@ -709,6 +709,16 @@ > allwinner,pull =3D ; > }; > =20 > + mmc3_8bit_emmc_pins: mmc3@1 { > + allwinner,pins =3D "PC6", "PC7", "PC8", "PC9", > + "PC10", "PC11", "PC12", > + "PC13", "PC14", "PC15", > + "PC24"; > + allwinner,function =3D "mmc3"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + Is that reset pin optional? If so, I'd prefer it to be a separate node, like we're doing for the SPI chip selects for example. It allows more reusability between different devices without declaring new nodes. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --XOIedfhf+7KOe/yw Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWopGqAAoJEBx+YmzsjxAgdjkP+wYP91OitTrfvbfTPpKbz2h2 2TJMrcTUesUjfgJVWl9SBH1otrKEKlNQNweumbyMp7bBPZjtEROrun3IetOLd9OS cSChIsoxWQMqtBL2Enm21TROZEDFXtNankFEL7tvOUqC1+DOTpJeo0FPCV5LchyT /2jp92bjL/a8KnMaBO0Uzvd9OTntPyeWxjmsswbqS7FukLgVvHmnDKN48Asb2bRf 6mtisLNflWwFIGhUFoTz450icvqS365h7fmNLhSC9DOos/tMLxhs4rMOeMj7Cr9i hJ3djaA4TJLev40LxELaLJGs/aP76To0q2PGvrvRnBp/zBXsZBDAr6+ox9XXA4dK AzSiYlCvwjMlGAye661G9xmz6w6CIeZZJ8S6cZtI1VMOqpbyEzAYO1ASep15s+V9 ZZAAZorCIYgiOlImnn/5vpPD+G76jZ/F8xH+ONqZeo2Sb6Jy0zqnzM1CdTjVYps/ WPMhM2TMqeiZ5gRj1+hBG0if9eSlw9RdsYZaKYd8X0oOwmDy2rjTv9Lqm9svGGsJ Vk+0Mu3izjfFtFb9aC41geRS8xkR4d6luR9HeEZOVPZXyUB0q7wjgiPiEzcZLjrE IIAi5CDVLW2+ZYnbCRRPr+wnHfYPL1loZoKluqTnz9Ua6rwHg3H5FPY1TAOk8Ina +A4+eg0RipPQ2fnrrGYJ =iBVh -----END PGP SIGNATURE----- --XOIedfhf+7KOe/yw--