From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754686AbcAVUjb (ORCPT ); Fri, 22 Jan 2016 15:39:31 -0500 Received: from down.free-electrons.com ([37.187.137.238]:55932 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754521AbcAVUj3 (ORCPT ); Fri, 22 Jan 2016 15:39:29 -0500 Date: Fri, 22 Jan 2016 21:39:27 +0100 From: Maxime Ripard To: Chen-Yu Tsai Cc: Ulf Hansson , Hans de Goede , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Message-ID: <20160122203927.GC3682@lukather> References: <1453354002-28366-1-git-send-email-wens@csie.org> <1453354002-28366-10-git-send-email-wens@csie.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="vOmOzSkFvhd7u8Ms" Content-Disposition: inline In-Reply-To: <1453354002-28366-10-git-send-email-wens@csie.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --vOmOzSkFvhd7u8Ms Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote: > According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC. > Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal > voltage sensing/switching, and "cap-mmc-hw-reset" to denote this > instance can use eMMC hardware reset. >=20 > Signed-off-by: Chen-Yu Tsai > --- > arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/bo= ot/dts/sun6i-a31s-sina31s-core.dtsi > index ea69fb8ad4d8..4ec0c8679b2e 100644 > --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi > +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi > @@ -61,12 +61,14 @@ > }; > =20 > /* eMMC on core board */ > -&mmc2 { > +&mmc3 { > pinctrl-names =3D "default"; > - pinctrl-0 =3D <&mmc2_8bit_emmc_pins>; > + pinctrl-0 =3D <&mmc3_8bit_emmc_pins>; > vmmc-supply =3D <®_dcdc1>; > + vqmmc-supply =3D <®_dcdc1>; That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could be either at 1.8 or 3V. Having the same regulator on both would make VCCQ forced to 3.3V, which seems to go against your commit log. What's the catch ? :) Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --vOmOzSkFvhd7u8Ms Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWopN/AAoJEBx+YmzsjxAgJd4P/jtf1+Ga0hcUK1KRbvSIC29s YKxfG2SkXpInxNejeOnPd0RQi2/z5b0O9jBJc1XHWweUP7OuM+Sbhv/jFQ5OSJ5i qAlKzLhGbgGtfiBsXHhfU21KqymERa/SvazHPBV9hzIow4atzBxaBVh5n4OwjOkE 2peO3DLhrbJ6sDpvu/fBHjVuszlN0BawHAu2DfixXLVVXykbligclAEVa3iGRo5y OzgPRIC/sJM64Hb9iG90NGhm2HLQfY+URiujKVyh4QspM8NAAOfTWbQFveeVIOK9 4hoIbQFnBUUHZ5NYemjlTsHk0xt7YWYJUbtIznXeJ4BRhzAiL/Cli96WhY/GFCGk 3oycKWq/+q7NaT0Bw3DYZiwq9I2A32bN45VxSQi7UkUFFiROFOgIpaAv/8PwYqgf UFhPtfEZ/RVh/o7MZcpCqhagyF6RuEspHY6IuQbBZYR26lKUQH7Q2xshP2HQ4Dt5 WVHIDBPPei8wvrhb7EW8YsQsqTFNedTX6ScPTlwAYo+GmkYGmvc5o1PrFyASEjGj FELXi/c1LYymCBPKUBF9UQhCSV8aAYhuoc4+kFYBeWGtW5Iw+gHX79sRkUTMAM6W gMfHCfvaOEG27Dz6L4Bj9znN7h1QjhR1yWsq1WIziporPTDQ6yeJtqCXV8A2VAv7 PsiD7LslVATUF/yUABcu =0aiJ -----END PGP SIGNATURE----- --vOmOzSkFvhd7u8Ms--