From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755161AbcA1GcY (ORCPT ); Thu, 28 Jan 2016 01:32:24 -0500 Received: from mail.kernel.org ([198.145.29.136]:35860 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754392AbcA1GcV (ORCPT ); Thu, 28 Jan 2016 01:32:21 -0500 Date: Thu, 28 Jan 2016 14:32:13 +0800 From: Shawn Guo To: Carlos Soto Cc: Sascha Hauer , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/1] imx25: Fix LCD pixelclock configuration Message-ID: <20160128063213.GJ9070@tiger> References: <1450902610-27224-1-git-send-email-csotoalonso@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1450902610-27224-1-git-send-email-csotoalonso@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 23, 2015 at 09:30:10PM +0100, Carlos Soto wrote: > Set LCDC base clock (per_7) parent clock to UPLL clock. > This is needed to allow finer resolution in pixelclock > > Signed-off-by: Carlos Soto > --- > drivers/clk/imx/clk-imx25.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c > index c4c141c..656340e 100644 > --- a/drivers/clk/imx/clk-imx25.c > +++ b/drivers/clk/imx/clk-imx25.c > @@ -238,6 +238,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, > clk_set_parent(clk[per5_sel], clk[ahb]); > > /* > + * set LCDC base clock (per 7) to highest possible frequency (UPLL) > + * to get best resolution for pixel clock > + */ > + clk_set_parent(clk[per7_sel], clk[upll]); This can be done in device tree via assigned-clock-parents without the need of touching kernel. Shawn > + > + /* > * Let's initially set up CLKO parent as ipg, since this configuration > * is used on some imx25 board designs to clock the audio codec. > */ > -- > 1.7.10.4 > >