From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756586AbcBCICM (ORCPT ); Wed, 3 Feb 2016 03:02:12 -0500 Received: from e06smtp11.uk.ibm.com ([195.75.94.107]:41367 "EHLO e06smtp11.uk.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755852AbcBCICJ (ORCPT ); Wed, 3 Feb 2016 03:02:09 -0500 X-IBM-Helo: d06dlp02.portsmouth.uk.ibm.com X-IBM-MailFrom: heiko.carstens@de.ibm.com X-IBM-RcptTo: linux-arch@vger.kernel.org;linux-kernel@vger.kernel.org;linux-s390@vger.kernel.org Date: Wed, 3 Feb 2016 09:01:59 +0100 From: Heiko Carstens To: Yury Norov Cc: linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, arnd@arndb.de, pinskia@gmail.com, Prasun.Kapoor@caviumnetworks.com, catalin.marinas@arm.com, Nathan_Lynch@mentor.com, linux-kernel@vger.kernel.org, agraf@suse.de, klimov.linux@gmail.com, broonie@kernel.org, joseph@codesourcery.com, schwidefsky@de.ibm.com, linux-arm-kernel@lists.infradead.org, christoph.muellner@theobroma-systems.com Subject: Re: [PATCH 1/5] all: s390: move wrapper infrastructure to generic headers Message-ID: <20160203080159.GA3369@osiris> References: <1453741047-5498-1-git-send-email-ynorov@caviumnetworks.com> <1453741047-5498-2-git-send-email-ynorov@caviumnetworks.com> <20160128121618.GB5418@osiris> <20160128163109.GA8529@yury-N73SV> <20160201114251.GB973@yury-N73SV> <20160202073913.GB3990@osiris> <20160202154331.GA3003@yury-N73SV> <20160202160826.GF3990@osiris> <20160202195434.GA3397@osiris> <20160202204156.GA27290@yury-N73SV> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160202204156.GA27290@yury-N73SV> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16020308-0041-0000-0000-0000075FDD9F Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 02, 2016 at 11:41:56PM +0300, Yury Norov wrote: > On Tue, Feb 02, 2016 at 08:54:34PM +0100, Heiko Carstens wrote: > > So I think I can summarize my point to: if you can enforce correctness, why > > shouldn't you do it if the performance impact is only a single instruction. > > For aarch64 it's 5 instructions. But what's more important (if ever), > another wrapper takes another i-cache line... > : > stp x29, x30, [sp,#-16]! > mov x29, sp > bl d40 > ldp x29, x30, [sp],#16 > ret Why does gcc allocate a stackframe here? Don't you have tail call optimization?