From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966293AbcBDQLi (ORCPT ); Thu, 4 Feb 2016 11:11:38 -0500 Received: from mga04.intel.com ([192.55.52.120]:59920 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965006AbcBDQLf (ORCPT ); Thu, 4 Feb 2016 11:11:35 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,396,1449561600"; d="scan'208";a="896403979" Date: Thu, 4 Feb 2016 18:11:28 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Lyude Cc: Daniel Vetter , Jani Nikula , David Airlie , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Benjamin Tissoires , Rob Clark Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Fix typo in DPLL_CFGCR1 definition Message-ID: <20160204161128.GO23290@intel.com> References: <1454600601-21900-1-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1454600601-21900-1-git-send-email-cpaul@redhat.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 04, 2016 at 10:43:21AM -0500, Lyude wrote: > We accidentally point both cfgcr registers for the second shared DPLL to > the same location in i915_reg.h. This results in a lot of hw pipe state > mismatches whenever we try to do a modeset that requires allocating the > DPLL to a CRTC: > > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x80000168, found 0x000004a5) > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 108000, found 49500) > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 108000, found 49500) > > This usually ends up causing blank monitors, since the DPLL never can > get set to the right clock. > > Fixes: f0f59a00a1 ("drm/i915: Type safe register read/write") Actually Fixes: 086f8e84a085 ("drm/i915: Prefix raw register defines with underscore") That's the second regression from the type safety stuff :( I guess we still don't have enough testing coverage since this has gone undetected for so long. Reviewed-by: Ville Syrjälä > Signed-off-by: Lyude > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 007ae83..b9a564b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7514,7 +7514,7 @@ enum skl_disp_power_wells { > #define DPLL_CFGCR2_PDIV_7 (4<<2) > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) > > -#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2) > +#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) > #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) > > /* BXT display engine PLL */ > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC