From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752390AbcBHK1A (ORCPT ); Mon, 8 Feb 2016 05:27:00 -0500 Received: from down.free-electrons.com ([37.187.137.238]:60310 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751590AbcBHK07 (ORCPT ); Mon, 8 Feb 2016 05:26:59 -0500 Date: Mon, 8 Feb 2016 11:26:56 +0100 From: Antoine Tenart To: Marc Zyngier Cc: Antoine Tenart , tglx@linutronix.de, jason@lakedaemon.net, tsahee@annapurnalabs.com, rshitrit@annapurnalabs.com, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/6] irqchip: add the Alpine MSIX interrupt controller Message-ID: <20160208102656.GA4117@kwain> References: <1454922971-17405-1-git-send-email-antoine.tenart@free-electrons.com> <1454922971-17405-2-git-send-email-antoine.tenart@free-electrons.com> <56B86391.1030609@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="jI8keyz6grp/JLjh" Content-Disposition: inline In-Reply-To: <56B86391.1030609@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --jI8keyz6grp/JLjh Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Marc, On Mon, Feb 08, 2016 at 09:44:49AM +0000, Marc Zyngier wrote: > On 08/02/16 09:16, Antoine Tenart wrote: > > + > > +/* MSIX message address format: local GIC target */ > > +#define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16) > > + > > +struct alpine_msix_data { > > + spinlock_t msi_map_lock; > > + u32 addr_high; > > + u32 addr_low; >=20 > As this looks to be a physical address, please consider using phys_addr_t. Sure. [=E2=80=A6] > > +static int alpine_msix_init(struct device_node *node, > > + struct device_node *parent) > > +{ > > + struct alpine_msix_data *priv; > > + struct resource res; > > + int ret; > > + > > + priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); > > + if (!priv) > > + return -ENOMEM; > > + > > + spin_lock_init(&priv->msi_map_lock); > > + > > + ret =3D of_address_to_resource(node, 0, &res); > > + if (ret) { > > + pr_err("Failed to allocate resource\n"); > > + goto err_priv; > > + } > > + > > + priv->addr_high =3D upper_32_bits((u64)res.start); > > + priv->addr_low =3D lower_32_bits(res.start) + ALPINE_MSIX_SPI_TARGET_= CLUSTER0; >=20 > This is a bit odd. If you always set bit 16, why isn't that reflected in > the base address coming from the DT? The 20 least significant bits of addr_low provide direct information regarding the interrupt destination, so I thought it would be clearer to have this explicitly in the driver so that we know what those bits mean. What do you think? Thanks for the review! Antoine --=20 Antoine T=C3=A9nart, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --jI8keyz6grp/JLjh Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBCgAGBQJWuG1wAAoJEFxNi8it27zYMqoP/RkJIrAa9KAoLY/71wn+Ary0 o98ilpgZRT97GddG7t6pghWVMbo9r4bbc3XmWCZBl7sMmdSVG2NAcDDAM9+TwRPS WowO5J2Gjy4HOoFWcZJxBzlSphOVXszSU+qT2SktT7zePVX4xd1F1Hz3Yuh1amWR hXYt7PrskSdecBgU6Swy2DSBFlQAoMw3FYwCrrvfHDalsupKtybTw0h/llWFqnFP 5gGt7elnuaJVx5ww7mRUhQ/I5BUwwUa1xpMMulLSEZQwT+IENd36Vytx87QW5QCM AhhfCUhgfrKhMHQKTgXOHtsvyX6v3+1cQ25PQsO3XWrrX4itqNF+fv3kx0YCcNVZ AX2iGCja/RIYnINYuKLKDqFkwYg5xlBXMlynhz7yjrZluyp/tQ8ow4er6wTx1iYA 7HgpqLy8mgWfZisOILPn+hYtcJZAsljcW2cKwRxaisDxjiLih3fZZWgzq6JbaBtE +WWLRpemJQujw0FbY+7TJ91I19v9cpYPLbQwTFBRWDSYA4LuN38NZ8GMfaiVyXJ5 fhoUgpEdJbbQ800ZfAevKO2vTDC2U5BdfXSPsjwkPb48ir0Q7VjquewVeYSr+Td1 0cPJI+cxcpx/Dr45j6AFN/EPjxIJNZGg8mLawoJ4aiYiQlKebcTgQ49SJlU+//In J4AgLnK0hmjodh25vpJk =aa1h -----END PGP SIGNATURE----- --jI8keyz6grp/JLjh--