From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751286AbcBHLCK (ORCPT ); Mon, 8 Feb 2016 06:02:10 -0500 Received: from down.free-electrons.com ([37.187.137.238]:33084 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750751AbcBHLCI (ORCPT ); Mon, 8 Feb 2016 06:02:08 -0500 Date: Mon, 8 Feb 2016 12:01:51 +0100 From: Antoine Tenart To: Marc Zyngier Cc: Antoine Tenart , tglx@linutronix.de, jason@lakedaemon.net, tsahee@annapurnalabs.com, rshitrit@annapurnalabs.com, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/6] irqchip: add the Alpine MSIX interrupt controller Message-ID: <20160208110151.GD4117@kwain> References: <1454922971-17405-1-git-send-email-antoine.tenart@free-electrons.com> <1454922971-17405-2-git-send-email-antoine.tenart@free-electrons.com> <56B86391.1030609@arm.com> <20160208102656.GA4117@kwain> <56B86EA8.9070306@arm.com> <20160208104407.GB4117@kwain> <56B87450.1040500@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="wLAMOaPNJ0fu1fTG" Content-Disposition: inline In-Reply-To: <56B87450.1040500@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --wLAMOaPNJ0fu1fTG Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Feb 08, 2016 at 10:56:16AM +0000, Marc Zyngier wrote: > On 08/02/16 10:44, Antoine Tenart wrote: > > On Mon, Feb 08, 2016 at 10:32:08AM +0000, Marc Zyngier wrote: > >> On 08/02/16 10:26, Antoine Tenart wrote: > >>>>> +static int alpine_msix_init(struct device_node *node, > >>>>> + struct device_node *parent) > >>>>> +{ > >>>>> + struct alpine_msix_data *priv; > >>>>> + struct resource res; > >>>>> + int ret; > >>>>> + > >>>>> + priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); > >>>>> + if (!priv) > >>>>> + return -ENOMEM; > >>>>> + > >>>>> + spin_lock_init(&priv->msi_map_lock); > >>>>> + > >>>>> + ret =3D of_address_to_resource(node, 0, &res); > >>>>> + if (ret) { > >>>>> + pr_err("Failed to allocate resource\n"); > >>>>> + goto err_priv; > >>>>> + } > >>>>> + > >>>>> + priv->addr_high =3D upper_32_bits((u64)res.start); > >>>>> + priv->addr_low =3D lower_32_bits(res.start) + ALPINE_MSIX_SPI_TAR= GET_CLUSTER0; > >>>> > >>>> This is a bit odd. If you always set bit 16, why isn't that reflecte= d in > >>>> the base address coming from the DT? > >>> > >>> The 20 least significant bits of addr_low provide direct information > >>> regarding the interrupt destination, so I thought it would be clearer > >>> to have this explicitly in the driver so that we know what those bits > >>> mean. > >> > >> So what is this information? TARGET_CLUSTER0 is not very expressive, a= nd > >> doesn't show what the alternatives are. Could you please elaborate a b= it > >> on that front? > >=20 > > For now lots of bits are reserved, so there aren't many alternatives. > > Bits [18:17] are used to set the GIC to which to route the MSI and bit > > 16 must be set when this target GIC is the primary GIC (bits [18:17] set > > to 0x0). There aren't other options available for now (that I'm aware > > of) for the target GIC configuration. >=20 > OK. So maybe add that as a comment, so that people know what is > happening there. And if the code gets updated to include new > functionalities, it will be easier to track the changes. OK, I'll update. Antoine --=20 Antoine T=E9nart, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --wLAMOaPNJ0fu1fTG Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBCgAGBQJWuHWfAAoJEFxNi8it27zYYCAQAJALX/VL1ihf9hHugB3MbeJ2 jfH3wD2y4GU4jdvwHml9xYor4SBt2HwbkKTXmtt50RUdKgDMihKtcejTR93+iyCy cBy05S2eraT9WX1XdSxqAWTXjVrOk4fj76Gnu/3FBVdbPpXOHYEBZQJemrROY4CL c3fhbXtQzoNEaOmK5O6Zw0Wer3xnK6fibKgkhLy3gxusuBce1gaLIFZMtDa9sKLV N2924bJb48SYg11NKBhAvIo/6B8Wft2oP6R5Oz1qbm2vHZ4wU+Q9DEQaWdouHTW4 g7BfpkFM1why1ZQ7NyImKHypjaDE1pNiWitH80rr7j10WdgJ881Qd01j/ji6GkPn 6+Vd+Qp7gliXob+xNiF5y5gGyt+SzZ3QM8nM0HgLcJPTgVNi3C5dOlC+ZarBK7cc HN1JC7w6UxIP1YIIrmp3xvtzlxJGmQlU9p5mckT3tY/n75AjCIXPWsPo6UIRjsXE 4bdzG6F99uFjUQ6H1IuZUb6IHBKJn0n19Lj2vHisBo9533YyZigYS3QGD/ZHKSL0 LOu3UOGXG0TWXpT6c3wjeCYlEaEvpzjKczJWXKwHhEZj64ubZTiFXnWpenN+ljRb w2fGOddPW2t+G5wva8g+p1We3uUD0D7wBTO1vMGMyCLRLz4hPEVWXEDNPGZlfXiz qdFC3/Qv1yyS2xsqRiwF =XHNK -----END PGP SIGNATURE----- --wLAMOaPNJ0fu1fTG--