From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753895AbcBHOsi (ORCPT ); Mon, 8 Feb 2016 09:48:38 -0500 Received: from down.free-electrons.com ([37.187.137.238]:39286 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753471AbcBHOsh (ORCPT ); Mon, 8 Feb 2016 09:48:37 -0500 Date: Mon, 8 Feb 2016 15:48:34 +0100 From: Antoine Tenart To: Marc Zyngier Cc: Antoine Tenart , Thomas Gleixner , jason@lakedaemon.net, tsahee@annapurnalabs.com, rshitrit@annapurnalabs.com, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/6] irqchip: add the Alpine MSIX interrupt controller Message-ID: <20160208144834.GH4117@kwain> References: <1454922971-17405-1-git-send-email-antoine.tenart@free-electrons.com> <1454922971-17405-2-git-send-email-antoine.tenart@free-electrons.com> <20160208141754.GG4117@kwain> <56B8A638.1040903@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="l06SQqiZYCi8rTKz" Content-Disposition: inline In-Reply-To: <56B8A638.1040903@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --l06SQqiZYCi8rTKz Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Feb 08, 2016 at 02:29:12PM +0000, Marc Zyngier wrote: > On 08/02/16 14:17, Antoine Tenart wrote: > > Thomas, > >=20 > > On Mon, Feb 08, 2016 at 11:31:47AM +0100, Thomas Gleixner wrote: > >> On Mon, 8 Feb 2016, Antoine Tenart wrote: > >>> +static int alpine_msix_set_affinity(struct irq_data *irq_data, > >>> + const struct cpumask *mask, bool force) > >>> +{ > >>> + int ret; > >>> + > >>> + ret =3D irq_chip_set_affinity_parent(irq_data, mask, force); > >>> + return ret =3D=3D IRQ_SET_MASK_OK ? IRQ_SET_MASK_OK_DONE : ret; > >> > >> What's the point of this exercise? Why can't you just set the affinity > >> callback to irq_chip_set_affinity_parent() ? > >=20 > > That's what done in irq-gic-v2m.c. Besides that, I see no point. I'll > > update for v2. >=20 > That's because there is no need to do another compose_msi_msg/write_msg > in msi_domain_set_affinity() once the affinity has been updated at the > GIC level. Alternatively, updating the GIC driver to always return > IRQ_SET_MASK_OK_DONE would be perfectly acceptable. I'm using drivers/irqchip/irq-gic-v3.c which is indeed always returning IRQ_SET_MASK_OK. I'll make a new patch in the v2 of this series to return IRQ_SET_MASK_OK_DONE instead in the GIC driver (and then patch irq-gic-v2m.c). Thanks, Antoine --=20 Antoine T=E9nart, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --l06SQqiZYCi8rTKz Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBCgAGBQJWuKrBAAoJEFxNi8it27zYEdkP/jZNpSc25pEU6R0N1IufnE1A xn2XDr2p26DGRyanZK9g4Hmc0IcT6DHdF5KXyYR3UnOPubUSGj3F2KLasO51I/w6 hF3zAuHvRnXYdWFOrYUGz4Kmkj50XkTLeieyitQWY5HA9Razp0KgcnFfb+1enluU Cq1hechWfDZsd3ivu0/wj27O/da6I3U5fgXRz7v5rkKwcYIsRosg+9GbzlSyjZ2A cvF27WKcVK6pjmnQ+ZsQzoJshaHfo/TlbwL/rIv93fr63pvny1M7qD3UUNIlor35 k+HrJVY9y+3X/o7NYWFCHGg1UEQpc8zhea/w7/PUo5IRAm9JlCQPRppZC4LImcSO Muv+ol9ZabX+D+w5KfUdIvhXqAY61GzKgfOJr4OC10g9kFcY96xYUtWG3crmbr4n MIvISprLAGnHbvxRJIpTn3+NHn1BNtMg6ele68g0vfeOOLu+8pOE0cHEN3NTlJ0F DQR/ROJJJ1r5kKT4iOQpogIlrBaMdPi100mo7So1kAGry/uMcyMCv4EusfhhuDPG 4YlNNl0mbJIkP7kHGTLzuaKE61HEAElCnvDNiX6ojksyOdPdASQ9EY0/Bpo2daWw xNb4AUCouY6G3u4AhiLmlcQ5qfMMnOLnOslEXJ75F1mFIr+m6nZrBSMit/vhTE7j /StRhWg4OkWtCG/gE+T+ =11y1 -----END PGP SIGNATURE----- --l06SQqiZYCi8rTKz--