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Date: Thu, 11 Feb 2016 12:55:39 +0100
From: Borislav Petkov <bp@alien8.de>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: Ingo Molnar <mingo@kernel.org>, Andrew Morton <akpm@linux-foundation.org>,
        Andy Lutomirski <luto@kernel.org>,
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        Brian Gerst <brgerst@gmail.com>, linux-kernel@vger.kernel.org,
        linux-mm@kvack.org, linux-nvdimm@ml01.01.org, x86@kernel.org
Subject: Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for
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Message-ID: <20160211115539.GD5565@pd.tnic>
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On Wed, Feb 10, 2016 at 11:27:50AM -0800, Luck, Tony wrote:
> Digging in the data sheet I found the CAPID0 register which does
> indicate in bit 4 whether this is an "EX" (a.k.a. "E7" part). But
> we invent a new PCI device ID for this every generation (0x0EC3 in
> Ivy Bridge, 0x2fc0 in Haswell, 0x6fc0 in Broadwell). The offset
> has stayed at 0x84 through all this.
> 
> I don't think that hunting the ever-changing PCI-id is a
> good choice ...

Right :-\

> the "E5/E7" naming convention has stuck for
> four generations[1] (Sandy Bridge, Ivy Bridge, Haswell, Broadwell).
> 
> -Tony
> 
> [1] Although this probably means that marketing are about to
> think of something new ... they generally do when people start
> understanding the model names :-(

Yeah, customers shouldn't slack and relax into even thinking they know
the model names. Fortunately there's wikipedia...

Thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.