From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933135AbcBPW4L (ORCPT ); Tue, 16 Feb 2016 17:56:11 -0500 Received: from mail-pf0-f178.google.com ([209.85.192.178]:34972 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756309AbcBPW4G convert rfc822-to-8bit (ORCPT ); Tue, 16 Feb 2016 17:56:06 -0500 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT To: Caesar Wang , "Heiko Stuebner" , edubezval@gmail.com From: Michael Turquette In-Reply-To: <1455521613-27340-3-git-send-email-wxt@rock-chips.com> Cc: huangtao@rock-chips.com, linux-pm@vger.kernel.org, "Stephen Boyd" , zhangqing@rock-chips.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, "Dmitry Torokhov" , "Jeffy Chen" , "Zhang Rui" , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Caesar Wang" References: <1455521613-27340-1-git-send-email-wxt@rock-chips.com> <1455521613-27340-3-git-send-email-wxt@rock-chips.com> Message-ID: <20160216224310.2278.75088@quark.deferred.io> User-Agent: alot/0.3.6 Subject: Re: [RESEND PATCH 2/8] clk: rockchip: add the tsadc clocks found on rk3228 SoCs Date: Tue, 16 Feb 2016 14:43:10 -0800 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Caesar Wang (2016-02-14 23:33:27) > This patch adds the needed clocks for rk3228 tsadc. > > Signed-off-by: Caesar Wang Acked-by: Michael Turquette > --- > > drivers/clk/rockchip/clk-rk3228.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c > index c515915..ac014b9 100644 > --- a/drivers/clk/rockchip/clk-rk3228.c > +++ b/drivers/clk/rockchip/clk-rk3228.c > @@ -424,7 +424,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { > GATE(0, "sclk_otgphy1", "xin24m", 0, > RK2928_CLKGATE_CON(1), 6, GFLAGS), > > - COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, > + COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, > RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, > RK2928_CLKGATE_CON(2), 8, GFLAGS), > > @@ -584,7 +584,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { > GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), > GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS), > GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS), > - GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS), > + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS), > GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS), > GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), > GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS), > -- > 1.9.1 >