From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1428012AbcBSP5c (ORCPT ); Fri, 19 Feb 2016 10:57:32 -0500 Received: from pmta2.delivery5.ore.mailhop.org ([54.186.218.12]:14210 "EHLO pmta2.delivery5.ore.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1427986AbcBSP5b (ORCPT ); Fri, 19 Feb 2016 10:57:31 -0500 X-MHO-User: aea3ec97-d721-11e5-8de6-958346fd02ba X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 74.98.178.100 X-Mail-Handler: DuoCircle Outbound SMTP X-DKIM: OpenDKIM Filter v2.6.8 io 47FA480047 Date: Fri, 19 Feb 2016 15:57:28 +0000 From: Jason Cooper To: Thomas Petazzoni Cc: Thomas Gleixner , Marc Zyngier , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Nadav Haklai , Lior Amsalem Subject: Re: [PATCH v3] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K Message-ID: <20160219155728.GD958@io.lakedaemon.net> References: <1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 19, 2016 at 02:34:43PM +0100, Thomas Petazzoni wrote: > This commits adds a new irqchip driver that handles the ODMI > controller found on Marvell 7K/8K processors. The ODMI controller > provide MSI interrupt functionality to on-board peripherals, much like > the GIC-v2m. > > Signed-off-by: Thomas Petazzoni > --- > Changes v2 -> v2: > - Express NODMIS_SHIFT, NODMIS_PER_FRAME, NODMIS_MASK in term of each > other. Suggested by Marc Zyngier. > - Rework the global bitmask allocation to make sure we allocate a > number of longs rather than a number of bytes, to avoid having the > bitmap API (which operates on longs) access memory we haven't > explicitly allocated. Reported by Marc Zyngier. > > Changes v1 -> v2: > - Better commit title, as suggested by Marc Zyngier. > - Improve the DT binding documentation, as suggested by Marc Zingier: > add a reference to the GIC documentation, be more specific about > the marvell,spi-base values, and add the requirement of the > interrupt-parent property. > - As suggested by Marc Zyngier, use a single global bitmap to > allocate all ODMIs, regardless of the frame they belong to. As part > of this change, the hwirq used to identify the interrupt inside the > ODMI irqdomain are 0-based (instead of being based on their > corresponding SPI base value), which allows to significantly > simplify the allocation/free logic. > --- > .../marvell,odmi-controller.txt | 41 ++++ > drivers/irqchip/Kconfig | 4 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-mvebu-odmi.c | 248 +++++++++++++++++++++ > 4 files changed, 294 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt > create mode 100644 drivers/irqchip/irq-mvebu-odmi.c Applied to irqchip/mvebu with Marc's Reviewed-by. thx, Jason.