From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758757AbcBXUXS (ORCPT ); Wed, 24 Feb 2016 15:23:18 -0500 Received: from down.free-electrons.com ([37.187.137.238]:56562 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758695AbcBXUXP (ORCPT ); Wed, 24 Feb 2016 15:23:15 -0500 Date: Wed, 24 Feb 2016 21:23:12 +0100 From: Antoine Tenart To: Marc Zyngier Cc: Antoine Tenart , tglx@linutronix.de, jason@lakedaemon.net, tsahee@annapurnalabs.com, rshitrit@annapurnalabs.com, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/7] irqchip: introduce the Alpine MSIX driver Message-ID: <20160224202312.GC29884@kwain> References: <1455895369-13187-1-git-send-email-antoine.tenart@free-electrons.com> <20160220104019.21e425c6@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="hYooF8G/hrfVAmum" Content-Disposition: inline In-Reply-To: <20160220104019.21e425c6@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --hYooF8G/hrfVAmum Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Marc, On Sat, Feb 20, 2016 at 10:40:19AM +0000, Marc Zyngier wrote: > On Fri, 19 Feb 2016 16:22:42 +0100 > Antoine Tenart wrote: > >=20 > > This series introduce the Alpine MSIX driver, and enables it in both > > the Alpine v1 and Alpine v2 device trees. > >=20 > > This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine supp= ort": > > https://lkml.org/lkml/2016/2/10/83 > >=20 > > You can find the series at: > > https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix > >=20 > > Antoine > >=20 > > Since v2: > > - Updated the documentation (added a reference to the GIC documentati= on). > >=20 > > Since v1: > > - Added an interrupt-parent property in the documentation example. > > - Updated to use bitmap_*() instead of *_bit(). > > - Removed the static irq_set_affinity to use irq_chip_set_affinity_pa= rent(). > > - Updated the address field to use phys_addr_t. > > - Added a comment on why we're setting bit 16 in the address. > > - Patched the gic_set_affinity() function in irqchip/gic-v3. > >=20 > > Antoine Tenart (7): > > irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity > > irqchip: add the Alpine MSIX interrupt controller > > Documentation: bindings: document the Alpine MSIX driver > > arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi > > ARM: dts: alpine: add the MSIX node > > arm64: alpine: select the Alpine MSI controller driver > > arm: alpine: select the Alpine MSI controller driver > >=20 > > .../interrupt-controller/al,alpine-msix.txt | 26 ++ > > arch/arm/boot/dts/alpine.dtsi | 10 + > > arch/arm/mach-alpine/Kconfig | 1 + > > arch/arm64/Kconfig.platforms | 1 + > > arch/arm64/boot/dts/al/alpine-v2.dtsi | 10 + > > drivers/irqchip/Kconfig | 6 + > > drivers/irqchip/Makefile | 1 + > > drivers/irqchip/irq-alpine-msi.c | 293 +++++++++++++= ++++++++ > > drivers/irqchip/irq-gic-v3.c | 2 +- > > 9 files changed, 349 insertions(+), 1 deletion(-) > > create mode 100644 Documentation/devicetree/bindings/interrupt-control= ler/al,alpine-msix.txt > > create mode 100644 drivers/irqchip/irq-alpine-msi.c > >=20 >=20 > I've queued the first three patches in my irq/gic-4.6 branch. I'd > expect the last 4 patches to be taken care off by armsoc once the code > has made it into Linus' tree. I'm taking care of the Alpine patches for 4.6, so I'll take the last 4 myself (and ensure their dependencies are met). Antoine --=20 Antoine T=E9nart, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --hYooF8G/hrfVAmum Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBCgAGBQJWzhEvAAoJEFxNi8it27zYUlAP/A0OYZyQesjD3c0ySqb6TIVO qnNF84/upbt4zMobv7vTraLyzfvS19hFQ+Vomp45Ng9r/7I+ACYYtY1hhmXB1Se/ T/bcZwp26ROHT47WDMrHPCxXuH9flhetqSrOwdYR/M6nn7SlFYKxhbwwi8QVrtJQ r/fMowvKxiI7Xvrl4wNZ/aVgbV1mwut8K7Y/FnnhER3u3T2rQ1Ic/ZV79A3ncea/ D9ClN9IQdoDSH3iwUwOw4mImZCY+1t+6inzgK2YohsWKRIejRNXjrs428joOcrhS stybeEDyYacvH4CEjF0qgEog2+/qdQ9ow/vsCmsvcnU9Su/w2pMUucL1ghSMsYl4 GV1typY+RvTabcCJHwRvhZ19CcyZbdNoBOwnJxUXJBGW7nzToPz0uNfCE63g3cvz BjSF5URIPsn5apeoLkjFZB228V0e+xZOUPeH8YVFrexIX60Fp3lkk5AsUQ3a/u+v +SiyfFFcHyy99F/oGS9PxJkmLzlcoPgapz+AyBAxYVHWVwGw8Px01s+xqlyw+w0D trJIzw3KFO0Eu9JAOFHK3bmsZPn/6mkApTBBQrH1jgInSpJc/SNIa3Jww5SMtrLg t5faoLWg/RQrsVNWzH+XxtluyRJlpgOHkOhZVqPw8W22wMh/TZQxqXvO7Js+QSvC 7pVmV/qe4U1z7D95k8mN =Dm56 -----END PGP SIGNATURE----- --hYooF8G/hrfVAmum--