* [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's
[not found] <cover.1456698862.git.henry@nitronetworks.nl>
@ 2016-02-28 23:13 ` Henry Paulissen
2016-03-01 4:43 ` Maxime Ripard
2016-03-08 9:01 ` Linus Walleij
2016-02-28 23:13 ` [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins Henry Paulissen
1 sibling, 2 replies; 6+ messages in thread
From: Henry Paulissen @ 2016-02-28 23:13 UTC (permalink / raw)
To: linux-sunxi
Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Hongzhou Yang,
Fabian Frederick, Patrice Chotard,
open list:PIN CONTROL SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support, open list
While I was testing irq's on the cubietruck I found a couple of
not working irq pins. Further diving into the problem it opened
up a mess called "manual".
This so called manual (A20 user manual v1.3 dated 2014-10-10) says:
Pin overview:
Page 233: EINT12 is on pin PC19 mux6.
Page 236: EINT12 is on pin PH12 mux6.
Now, it is a bit strange to have the same IRQ on 2 different pins,
but I guess this could still be possible hardware wise. But then:
Pin registers:
Page 253: EINT12 is *not* on pin PC19.
Page 281: EINT12 is on pin PH12.
The manual is so contradicting that further tests had to be made
to see which of the 2 statements where correct.
This patch is based on actual outcome of these tests and not what
the manual says.
Test procedure used:
Connect a 1 pulse per second (GPS) line to the pin.
echo pin### > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio###/direction
echo rising > /sys/class/gpio/gpio###/edge
Check /proc/interrupts if a irq was attached and if irq's where
received.
Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..25748b4 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins
[not found] <cover.1456698862.git.henry@nitronetworks.nl>
2016-02-28 23:13 ` [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's Henry Paulissen
@ 2016-02-28 23:13 ` Henry Paulissen
2016-03-01 4:42 ` Maxime Ripard
2016-03-08 9:03 ` Linus Walleij
1 sibling, 2 replies; 6+ messages in thread
From: Henry Paulissen @ 2016-02-28 23:13 UTC (permalink / raw)
To: linux-sunxi
Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai,
Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, Lee Jones,
Fabian Frederick, open list:PIN CONTROL SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support, open list
While I was testing irq's on the cubietruck I found a couple of
not working irq pins. Further diving into the problem it opened
up a mess called "manual".
This so called manual (A20 user manual v1.3 dated 2014-10-10) says:
Pin overview:
Page 237: EINT26 is on mux 5.
Page 288: EINT26 is on mux 6.
The manual is so contradicting that further tests had to be made
to see which of the 2 statements where correct.
This patch is based on actual outcome of these tests and not what
the manual says.
Test procedure used:
Connect a 1 pulse per second (GPS) line to the pin.
echo pin### > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio###/direction
echo rising > /sys/class/gpio/gpio###/edge
Check /proc/interrupts if a irq was attached and if irq's where
received.
Hardware used:
Henry Paulissen: Cubietruck
Andere Przywara: BananaPi M1
Tested-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index 25748b4..435ad30 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -956,65 +956,65 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins
2016-02-28 23:13 ` [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins Henry Paulissen
@ 2016-03-01 4:42 ` Maxime Ripard
2016-03-08 9:03 ` Linus Walleij
1 sibling, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2016-03-01 4:42 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, Linus Walleij, Chen-Yu Tsai,
Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, Lee Jones,
Fabian Frederick, open list:PIN CONTROL SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support, open list
[-- Attachment #1: Type: text/plain, Size: 1381 bytes --]
On Mon, Feb 29, 2016 at 12:13:27AM +0100, Henry Paulissen wrote:
> While I was testing irq's on the cubietruck I found a couple of
> not working irq pins. Further diving into the problem it opened
> up a mess called "manual".
>
> This so called manual (A20 user manual v1.3 dated 2014-10-10) says:
>
> Pin overview:
> Page 237: EINT26 is on mux 5.
> Page 288: EINT26 is on mux 6.
>
> The manual is so contradicting that further tests had to be made
> to see which of the 2 statements where correct.
>
> This patch is based on actual outcome of these tests and not what
> the manual says.
>
> Test procedure used:
>
> Connect a 1 pulse per second (GPS) line to the pin.
>
> echo pin### > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio###/direction
> echo rising > /sys/class/gpio/gpio###/edge
>
> Check /proc/interrupts if a irq was attached and if irq's where
> received.
>
> Hardware used:
> Henry Paulissen: Cubietruck
> Andere Przywara: BananaPi M1
>
> Tested-by: Andre Przywara <andre.przywara@arm.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks !
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's
2016-02-28 23:13 ` [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's Henry Paulissen
@ 2016-03-01 4:43 ` Maxime Ripard
2016-03-08 9:01 ` Linus Walleij
1 sibling, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2016-03-01 4:43 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, Linus Walleij, Chen-Yu Tsai, Hongzhou Yang,
Fabian Frederick, Patrice Chotard,
open list:PIN CONTROL SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support, open list
[-- Attachment #1: Type: text/plain, Size: 1472 bytes --]
On Mon, Feb 29, 2016 at 12:13:26AM +0100, Henry Paulissen wrote:
> While I was testing irq's on the cubietruck I found a couple of
> not working irq pins. Further diving into the problem it opened
> up a mess called "manual".
>
> This so called manual (A20 user manual v1.3 dated 2014-10-10) says:
>
> Pin overview:
> Page 233: EINT12 is on pin PC19 mux6.
> Page 236: EINT12 is on pin PH12 mux6.
>
> Now, it is a bit strange to have the same IRQ on 2 different pins,
> but I guess this could still be possible hardware wise. But then:
>
> Pin registers:
> Page 253: EINT12 is *not* on pin PC19.
> Page 281: EINT12 is on pin PH12.
>
> The manual is so contradicting that further tests had to be made
> to see which of the 2 statements where correct.
>
> This patch is based on actual outcome of these tests and not what
> the manual says.
>
> Test procedure used:
>
> Connect a 1 pulse per second (GPS) line to the pin.
>
> echo pin### > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio###/direction
> echo rising > /sys/class/gpio/gpio###/edge
>
> Check /proc/interrupts if a irq was attached and if irq's where
> received.
>
> Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's
2016-02-28 23:13 ` [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's Henry Paulissen
2016-03-01 4:43 ` Maxime Ripard
@ 2016-03-08 9:01 ` Linus Walleij
1 sibling, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2016-03-08 9:01 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Hongzhou Yang,
Fabian Frederick, Patrice Chotard,
open list:PIN CONTROL SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support, open list
On Mon, Feb 29, 2016 at 6:13 AM, Henry Paulissen <henry@nitronetworks.nl> wrote:
> While I was testing irq's on the cubietruck I found a couple of
> not working irq pins. Further diving into the problem it opened
> up a mess called "manual".
>
> This so called manual (A20 user manual v1.3 dated 2014-10-10) says:
>
> Pin overview:
> Page 233: EINT12 is on pin PC19 mux6.
> Page 236: EINT12 is on pin PH12 mux6.
>
> Now, it is a bit strange to have the same IRQ on 2 different pins,
> but I guess this could still be possible hardware wise. But then:
>
> Pin registers:
> Page 253: EINT12 is *not* on pin PC19.
> Page 281: EINT12 is on pin PH12.
>
> The manual is so contradicting that further tests had to be made
> to see which of the 2 statements where correct.
>
> This patch is based on actual outcome of these tests and not what
> the manual says.
>
> Test procedure used:
>
> Connect a 1 pulse per second (GPS) line to the pin.
>
> echo pin### > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio###/direction
> echo rising > /sys/class/gpio/gpio###/edge
>
> Check /proc/interrupts if a irq was attached and if irq's where
> received.
>
> Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins
2016-02-28 23:13 ` [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins Henry Paulissen
2016-03-01 4:42 ` Maxime Ripard
@ 2016-03-08 9:03 ` Linus Walleij
1 sibling, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2016-03-08 9:03 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai,
Jean-Christophe PLAGNIOL-VILLARD, Hongzhou Yang, Lee Jones,
Fabian Frederick, open list:PIN CONTROL SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support, open list
On Mon, Feb 29, 2016 at 6:13 AM, Henry Paulissen <henry@nitronetworks.nl> wrote:
> While I was testing irq's on the cubietruck I found a couple of
> not working irq pins. Further diving into the problem it opened
> up a mess called "manual".
>
> This so called manual (A20 user manual v1.3 dated 2014-10-10) says:
>
> Pin overview:
> Page 237: EINT26 is on mux 5.
> Page 288: EINT26 is on mux 6.
>
> The manual is so contradicting that further tests had to be made
> to see which of the 2 statements where correct.
>
> This patch is based on actual outcome of these tests and not what
> the manual says.
>
> Test procedure used:
>
> Connect a 1 pulse per second (GPS) line to the pin.
>
> echo pin### > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio###/direction
> echo rising > /sys/class/gpio/gpio###/edge
>
> Check /proc/interrupts if a irq was attached and if irq's where
> received.
>
> Hardware used:
> Henry Paulissen: Cubietruck
> Andere Przywara: BananaPi M1
>
> Tested-by: Andre Przywara <andre.przywara@arm.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
Patch applied with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <cover.1456698862.git.henry@nitronetworks.nl>
2016-02-28 23:13 ` [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's Henry Paulissen
2016-03-01 4:43 ` Maxime Ripard
2016-03-08 9:01 ` Linus Walleij
2016-02-28 23:13 ` [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins Henry Paulissen
2016-03-01 4:42 ` Maxime Ripard
2016-03-08 9:03 ` Linus Walleij
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