Re: [BUG] Core2 cpu triggers hard lockup with perf test

Peter Zijlstra
2016-03-01T18:12:18Z

On Tue, Mar 01, 2016 at 06:17:22PM +0100, Jiri Olsa wrote:
> I tried what Andy suggested below (not sure what he meant by Merom,
> I took PEBS format0 instead), works for me

Model 15, see intel_pmu_init(). But you're actually running on a Penryn
I suspect, since we disabled PEBS for Merom.

There's also a bunch of Atoms that uses PEBS format 0, no idea if
they're affected too.

> ---
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index c8a243d6fc82..c4a1a769bae7 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -269,7 +269,7 @@ static int alloc_pebs_buffer(int cpu)
> if (!x86_pmu.pebs)
> return 0;
>
> - buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
> + buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
> if (unlikely(!buffer))
> return -ENOMEM;
>
> @@ -286,7 +286,7 @@ static int alloc_pebs_buffer(int cpu)
> per_cpu(insn_buffer, cpu) = ibuffer;
> }
>
> - max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
> + max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
>
> ds->pebs_buffer_base = (u64)(unsigned long)buffer;
> ds->pebs_index = ds->pebs_buffer_base;
> @@ -1319,6 +1319,7 @@ void __init intel_ds_init(void)
>
> x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
> x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
> + x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
> if (x86_pmu.pebs) {
> char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
> int format = x86_pmu.intel_cap.pebs_format;
> @@ -1327,6 +1328,7 @@ void __init intel_ds_init(void)
> case 0:
> pr_cont("PEBS fmt0%c, ", pebs_type);
> x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);

At the very least this wants a comment along the lines of:

/*
* Using >PAGE_SIZE buffers makes the WRMSR to
* PERF_GLOBAL_CTRL in intel_pmu_enable_all()
* mysteriously hang on Core2.
*
* As a workaround, we don't do this.
*/

> + x86_pmu.pebs_buffer_size = PAGE_SIZE;
> x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
> break;
>
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index 7bb61e32fb29..1ab6279fed1d 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -586,6 +586,7 @@ struct x86_pmu {
> pebs_broken :1,
> pebs_prec_dist :1;
> int pebs_record_size;
> + int pebs_buffer_size;
> void (*drain_pebs)(struct pt_regs *regs);
> struct event_constraint *pebs_constraints;
> void (*pebs_aliases)(struct perf_event *event);