* [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k
@ 2016-03-07 4:09 Chanho Min
2016-03-07 4:09 ` [PATCH 1/4] arm64: add Kconfig entry for LG1K SoC family Chanho Min
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Chanho Min @ 2016-03-07 4:09 UTC (permalink / raw)
To: arm
Cc: Catalin Marinas, Will Deacon, Arnd Bergmann, linux-kernel,
linux-arm-kernel, Jongsung Kim, Gunho Lee, Chanho Min
This is an initial series for supporting LG Electronics's lg1k SoCs,
based on ARM Cortex-A53, mainly used for digital TVs.
Chanho Min (4):
arm64: add Kconfig entry for LG1K SoC family
arm64: defconfig: enable ARCH_LG1K
arm64: dts: Add dts files for LG Electronics's lg1312 SoC
MAINTAINERS: add myself as ARM/LG1K maintainer
MAINTAINERS | 6 +
arch/arm64/Kconfig.platforms | 4 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/lg/Makefile | 5 +
arch/arm64/boot/dts/lg/lg1312-ref.dts | 26 +++
arch/arm64/boot/dts/lg/lg1312.dtsi | 346 +++++++++++++++++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
7 files changed, 389 insertions(+)
create mode 100644 arch/arm64/boot/dts/lg/Makefile
create mode 100644 arch/arm64/boot/dts/lg/lg1312-ref.dts
create mode 100644 arch/arm64/boot/dts/lg/lg1312.dtsi
--
1.7.9.5
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/4] arm64: add Kconfig entry for LG1K SoC family 2016-03-07 4:09 [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Chanho Min @ 2016-03-07 4:09 ` Chanho Min 2016-03-07 4:09 ` [PATCH 2/4] arm64: defconfig: enable ARCH_LG1K Chanho Min ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Chanho Min @ 2016-03-07 4:09 UTC (permalink / raw) To: arm Cc: Catalin Marinas, Will Deacon, Arnd Bergmann, linux-kernel, linux-arm-kernel, Jongsung Kim, Gunho Lee, Chanho Min This patch introduces ARCH_LG1K to enable LG Electronics's LG1K SoC family in Kconfig. Signed-off-by: Chanho Min <chanho.min@lge.com> --- arch/arm64/Kconfig.platforms | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f6..b002bba 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -141,4 +141,8 @@ config ARCH_ZYNQMP help This enables support for Xilinx ZynqMP Family +config ARCH_LG1K + bool "LG Electronics LG1K SoC Family" + help + This enables support for LG Electronics LG1K SoC Family endmenu -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] arm64: defconfig: enable ARCH_LG1K 2016-03-07 4:09 [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Chanho Min 2016-03-07 4:09 ` [PATCH 1/4] arm64: add Kconfig entry for LG1K SoC family Chanho Min @ 2016-03-07 4:09 ` Chanho Min 2016-03-07 4:09 ` [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC Chanho Min ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Chanho Min @ 2016-03-07 4:09 UTC (permalink / raw) To: arm Cc: Catalin Marinas, Will Deacon, Arnd Bergmann, linux-kernel, linux-arm-kernel, Jongsung Kim, Gunho Lee, Chanho Min Enable building LG1K support in the defconfig. Signed-off-by: Chanho Min <chanho.min@lge.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 86581f7..14dbe27 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -49,6 +49,7 @@ CONFIG_ARCH_UNIPHIER=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y CONFIG_ARCH_ZYNQMP=y +CONFIG_ARCH_LG1K=y CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_IOV=y -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC 2016-03-07 4:09 [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Chanho Min 2016-03-07 4:09 ` [PATCH 1/4] arm64: add Kconfig entry for LG1K SoC family Chanho Min 2016-03-07 4:09 ` [PATCH 2/4] arm64: defconfig: enable ARCH_LG1K Chanho Min @ 2016-03-07 4:09 ` Chanho Min 2016-03-07 1:59 ` Mark Rutland 2016-03-07 4:26 ` Arnd Bergmann 2016-03-07 4:10 ` [PATCH 4/4] MAINTAINERS: add myself as ARM/LG1K maintainer Chanho Min 2016-03-07 4:29 ` [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Arnd Bergmann 4 siblings, 2 replies; 10+ messages in thread From: Chanho Min @ 2016-03-07 4:09 UTC (permalink / raw) To: arm Cc: Catalin Marinas, Will Deacon, Arnd Bergmann, linux-kernel, linux-arm-kernel, Jongsung Kim, Gunho Lee, Chanho Min Add initial dtsi file to support lg1312 SoC which based on Cortex-A53. Also add dts file to support lg1312 reference board which based on lg1312 SoC. Signed-off-by: Chanho Min <chanho.min@lge.com> --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/lg/Makefile | 5 + arch/arm64/boot/dts/lg/lg1312-ref.dts | 26 +++ arch/arm64/boot/dts/lg/lg1312.dtsi | 346 +++++++++++++++++++++++++++++++++ 4 files changed, 378 insertions(+) create mode 100644 arch/arm64/boot/dts/lg/Makefile create mode 100644 arch/arm64/boot/dts/lg/lg1312-ref.dts create mode 100644 arch/arm64/boot/dts/lg/lg1312.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f832b8a..90ce525 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -16,6 +16,7 @@ dts-dirs += rockchip dts-dirs += socionext dts-dirs += sprd dts-dirs += xilinx +dts-dirs += lg subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makefile new file mode 100644 index 0000000..b0cc649 --- /dev/null +++ b/arch/arm64/boot/dts/lg/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/lg/lg1312-ref.dts b/arch/arm64/boot/dts/lg/lg1312-ref.dts new file mode 100644 index 0000000..a9b00f3 --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg1312-ref.dts @@ -0,0 +1,26 @@ +/* + * dts file for lg1312 Reference Board. + * + * Copyright (C) 2016, LG Electronics + */ + +/dts-v1/; + +#include "lg1312.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <1>; + + model = "LG Electronics, DTV SoC LG1312 Reference Board"; + compatible = "lge,lg1312-ref", "lge,lg1312"; + + memory { + device_type = "memory"; + reg = <0x0 0x00000000 0x20000000>; + }; + + chosen { + bootargs = "root=/dev/nfs ip=dhcp"; + }; +}; diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi new file mode 100644 index 0000000..3146dbd --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -0,0 +1,346 @@ +/* + * dts file for lg1312 SoC + * + * Copyright (C) 2016, LG Electronics + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#define ARMV8_TIMER_IRQ_TYPE (GIC_CPU_MASK_RAW(0x0f) | IRQ_TYPE_LEVEL_LOW) + +/ { + #address-cells = <2>; + #size-cells = <1>; + + compatible = "lge,lg1312"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + + gic: interrupt-controller@c0001000 { + #interrupt-cells = <3>; + + compatible = "arm,gic-400"; + interrupt-controller; + reg = <0x0 0xc0001000 0x1000>, + <0x0 0xc0002000 0x1000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 ARMV8_TIMER_IRQ_TYPE>, + <GIC_PPI 14 ARMV8_TIMER_IRQ_TYPE>; + clock-frequency = <24000000>; + }; + + clocks { + clk_bus: clk_bus { + #clock-cells = <0>; + + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "BUSCLK"; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + eth0: ethernet@c1b00000 { + compatible = "cdns,gem"; + reg = <0x0 0xc1b00000 0x1000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "hclk", "pclk"; + phy-mode = "rmii"; + /* Filled in by boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + amba { + #address-cells = <2>; + #size-cells = <1>; + #interrupts-cells = <3>; + + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + timers: timer@fd100000 { + compatible = "arm,sp804"; + reg = <0x0 0xfd100000 0x1000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + wdog: watchdog@fd200000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xfd200000 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + uart0: serial@fe000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfe000000 0x1000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + uart1: serial@fe100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfe100000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + uart2: serial@fe200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfe200000 0x1000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + spi0: ssp@fe800000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xfe800000 0x1000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + spi1: ssp@fe900000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xfe900000 0x1000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + dmac0: dma@c1128000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xc1128000 0x1000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + gpio0: gpio@fd400000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd400000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio1: gpio@fd410000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd410000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio2: gpio@fd420000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd420000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio3: gpio@fd430000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd430000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + gpio4: gpio@fd440000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd440000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio5: gpio@fd450000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd450000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio6: gpio@fd460000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd460000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio7: gpio@fd470000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd470000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio8: gpio@fd480000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd480000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio9: gpio@fd490000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd490000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio10: gpio@fd4a0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4a0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio11: gpio@fd4b0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4b0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + gpio12: gpio@fd4c0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4c0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio13: gpio@fd4d0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4d0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio14: gpio@fd4e0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4e0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio15: gpio@fd4f0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4f0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio16: gpio@fd500000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd500000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio17: gpio@fd510000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd510000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + }; +}; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC 2016-03-07 4:09 ` [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC Chanho Min @ 2016-03-07 1:59 ` Mark Rutland 2016-03-09 10:21 ` Chanho Min 2016-03-07 4:26 ` Arnd Bergmann 1 sibling, 1 reply; 10+ messages in thread From: Mark Rutland @ 2016-03-07 1:59 UTC (permalink / raw) To: Chanho Min Cc: arm, Arnd Bergmann, Catalin Marinas, Gunho Lee, Will Deacon, linux-kernel, Jongsung Kim, linux-arm-kernel Hi, On Mon, Mar 07, 2016 at 01:09:59PM +0900, Chanho Min wrote: > Add initial dtsi file to support lg1312 SoC which based on > Cortex-A53. Also add dts file to support lg1312 reference board > which based on lg1312 SoC. > > Signed-off-by: Chanho Min <chanho.min@lge.com> I have a few comments on this patch below. > +/ { > + #address-cells = <2>; > + #size-cells = <1>; Is there definitely no reason to require a 64-bit size? e.g. ranges? Generally I'd expect both address and size to be described as 64 bit quantities in the root node, to make it less painful to extend in future. > + > + model = "LG Electronics, DTV SoC LG1312 Reference Board"; > + compatible = "lge,lg1312-ref", "lge,lg1312"; > + > + memory { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x20000000>; > + }; > + > + chosen { > + bootargs = "root=/dev/nfs ip=dhcp"; > + }; > +}; Drop these bootargs. This is specific to a particular developer's configuration, and they make no sense alone given the lack of an nfsroot, so they're evidently being overwritten anyway. > + psci { > + compatible = "arm,psci"; > + method = "smc"; > + cpu_suspend = <0x84000001>; > + cpu_off = <0x84000002>; > + cpu_on = <0x84000003>; > + }; What are you using as your PSCI implementation? Is it not PSCI 0.2+ compliant? Which exception level are you booting at? > + gic: interrupt-controller@c0001000 { > + #interrupt-cells = <3>; > + > + compatible = "arm,gic-400"; > + interrupt-controller; > + reg = <0x0 0xc0001000 0x1000>, > + <0x0 0xc0002000 0x1000>; > + }; I believe the CPU interface is too short (as GICC_DIR lives at 0x1000). What about GICH and GICV? > + pmu { > + compatible = "arm,armv8-pmuv3"; Use "arm,cortex-a53-pmu". > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 ARMV8_TIMER_IRQ_TYPE>, > + <GIC_PPI 14 ARMV8_TIMER_IRQ_TYPE>; > + clock-frequency = <24000000>; > + }; Please fix your firmware to program CNTFRQ. The clock-frequency property is at best a workaround for a broken system, and is not sufficient in general. > + clocks { > + clk_bus: clk_bus { > + #clock-cells = <0>; > + > + compatible = "fixed-clock"; > + clock-frequency = <198000000>; > + clock-output-names = "BUSCLK"; > + }; > + }; Just put this fixed-clock under the root node. There is nothing special about /clocks; it is not required to be probed and serves no purpose. Thanks, Mark. ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC 2016-03-07 1:59 ` Mark Rutland @ 2016-03-09 10:21 ` Chanho Min 0 siblings, 0 replies; 10+ messages in thread From: Chanho Min @ 2016-03-09 10:21 UTC (permalink / raw) To: 'Mark Rutland' Cc: arm, 'Arnd Bergmann', 'Catalin Marinas', 'Gunho Lee', 'Will Deacon', linux-kernel, 'Jongsung Kim', linux-arm-kernel > Hi, > > On Mon, Mar 07, 2016 at 01:09:59PM +0900, Chanho Min wrote: > > Add initial dtsi file to support lg1312 SoC which based on Cortex-A53. > > Also add dts file to support lg1312 reference board which based on > > lg1312 SoC. > > > > Signed-off-by: Chanho Min <chanho.min@lge.com> > > I have a few comments on this patch below. > > > +/ { > > + #address-cells = <2>; > > + #size-cells = <1>; > > Is there definitely no reason to require a 64-bit size? e.g. ranges? > > Generally I'd expect both address and size to be described as 64 bit > quantities in the root node, to make it less painful to extend in future. > > > + > > + model = "LG Electronics, DTV SoC LG1312 Reference Board"; > > + compatible = "lge,lg1312-ref", "lge,lg1312"; > > + > > + memory { > > + device_type = "memory"; > > + reg = <0x0 0x00000000 0x20000000>; > > + }; > > + > > + chosen { > > + bootargs = "root=/dev/nfs ip=dhcp"; > > + }; > > +}; > > Drop these bootargs. This is specific to a particular developer's > configuration, and they make no sense alone given the lack of an nfsroot, so > they're evidently being overwritten anyway. > > > + psci { > > + compatible = "arm,psci"; > > + method = "smc"; > > + cpu_suspend = <0x84000001>; > > + cpu_off = <0x84000002>; > > + cpu_on = <0x84000003>; > > + }; > > What are you using as your PSCI implementation? > > Is it not PSCI 0.2+ compliant? No, Our TZ firmware support for psci 0.1 only. > > Which exception level are you booting at? EL3. > > > + gic: interrupt-controller@c0001000 { > > + #interrupt-cells = <3>; > > + > > + compatible = "arm,gic-400"; > > + interrupt-controller; > > + reg = <0x0 0xc0001000 0x1000>, > > + <0x0 0xc0002000 0x1000>; > > + }; > > I believe the CPU interface is too short (as GICC_DIR lives at 0x1000). > > What about GICH and GICV? > > > + pmu { > > + compatible = "arm,armv8-pmuv3"; > > Use "arm,cortex-a53-pmu". > > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = <GIC_PPI 13 ARMV8_TIMER_IRQ_TYPE>, > > + <GIC_PPI 14 ARMV8_TIMER_IRQ_TYPE>; > > + clock-frequency = <24000000>; > > + }; > > Please fix your firmware to program CNTFRQ. > > The clock-frequency property is at best a workaround for a broken system, and > is not sufficient in general. > > > + clocks { > > + clk_bus: clk_bus { > > + #clock-cells = <0>; > > + > > + compatible = "fixed-clock"; > > + clock-frequency = <198000000>; > > + clock-output-names = "BUSCLK"; > > + }; > > + }; > > Just put this fixed-clock under the root node. There is nothing special about > /clocks; it is not required to be probed and serves no purpose. > > Thanks, > Mark. I'll resend this patch with fixes that you and Arnd mentioned. Thanks Chanho ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC 2016-03-07 4:09 ` [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC Chanho Min 2016-03-07 1:59 ` Mark Rutland @ 2016-03-07 4:26 ` Arnd Bergmann 1 sibling, 0 replies; 10+ messages in thread From: Arnd Bergmann @ 2016-03-07 4:26 UTC (permalink / raw) To: linux-arm-kernel Cc: Chanho Min, arm, Catalin Marinas, Gunho Lee, Will Deacon, linux-kernel, Jongsung Kim On Monday 07 March 2016, Chanho Min wrote: > + > + chosen { > + bootargs = "root=/dev/nfs ip=dhcp"; > + }; Can you add a stdout-path property as well, to make the console work? Please also include an aliases node in the .dts file. > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +#define ARMV8_TIMER_IRQ_TYPE (GIC_CPU_MASK_RAW(0x0f) | IRQ_TYPE_LEVEL_LOW) I would leave out the macro here and instead just open-code this in the place it is used. Arnd ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/4] MAINTAINERS: add myself as ARM/LG1K maintainer 2016-03-07 4:09 [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Chanho Min ` (2 preceding siblings ...) 2016-03-07 4:09 ` [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC Chanho Min @ 2016-03-07 4:10 ` Chanho Min 2016-03-07 4:29 ` [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Arnd Bergmann 4 siblings, 0 replies; 10+ messages in thread From: Chanho Min @ 2016-03-07 4:10 UTC (permalink / raw) To: arm Cc: Catalin Marinas, Will Deacon, Arnd Bergmann, linux-kernel, linux-arm-kernel, Jongsung Kim, Gunho Lee, Chanho Min Signed-off-by: Chanho Min <chanho.min@lge.com> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4f55edf..20ca61a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1245,6 +1245,12 @@ L: linux-kernel@vger.kernel.org S: Maintained F: drivers/memory/*emif* +ARM/LG1K ARCHITECTURE +M: Chanho Min <chanho.min@lge.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm64/boot/dts/lg/ + ARM/LOGICPD PXA270 MACHINE SUPPORT M: Lennert Buytenhek <kernel@wantstofly.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k 2016-03-07 4:09 [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Chanho Min ` (3 preceding siblings ...) 2016-03-07 4:10 ` [PATCH 4/4] MAINTAINERS: add myself as ARM/LG1K maintainer Chanho Min @ 2016-03-07 4:29 ` Arnd Bergmann 2016-03-07 6:45 ` Chanho Min 4 siblings, 1 reply; 10+ messages in thread From: Arnd Bergmann @ 2016-03-07 4:29 UTC (permalink / raw) To: linux-arm-kernel Cc: Chanho Min, arm, Catalin Marinas, Gunho Lee, Will Deacon, linux-kernel, Jongsung Kim On Monday 07 March 2016, Chanho Min wrote: > This is an initial series for supporting LG Electronics's lg1k SoCs, > based on ARM Cortex-A53, mainly used for digital TVs. > > Chanho Min (4): > arm64: add Kconfig entry for LG1K SoC family > arm64: defconfig: enable ARCH_LG1K > arm64: dts: Add dts files for LG Electronics's lg1312 SoC > MAINTAINERS: add myself as ARM/LG1K maintainer The patches look ok in principle, but the timing is unfortunate: we are at -rc7 now, just before the merge window, and we need to give this a little extra time for review, so I think we should merge this for 4.7, not 4.6. Arnd ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k 2016-03-07 4:29 ` [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Arnd Bergmann @ 2016-03-07 6:45 ` Chanho Min 0 siblings, 0 replies; 10+ messages in thread From: Chanho Min @ 2016-03-07 6:45 UTC (permalink / raw) To: 'Arnd Bergmann', linux-arm-kernel Cc: arm, 'Catalin Marinas', 'Gunho Lee', 'Will Deacon', linux-kernel, 'Jongsung Kim' > > The patches look ok in principle, but the timing is unfortunate: we are at - > rc7 now, just before the merge window, and we need to give this a little extra > time for review, so I think we should merge this for 4.7, not 4.6. It's ok for me. Chanho ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-03-09 10:22 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-03-07 4:09 [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Chanho Min 2016-03-07 4:09 ` [PATCH 1/4] arm64: add Kconfig entry for LG1K SoC family Chanho Min 2016-03-07 4:09 ` [PATCH 2/4] arm64: defconfig: enable ARCH_LG1K Chanho Min 2016-03-07 4:09 ` [PATCH 3/4] arm64: dts: Add dts files for LG Electronics's lg1312 SoC Chanho Min 2016-03-07 1:59 ` Mark Rutland 2016-03-09 10:21 ` Chanho Min 2016-03-07 4:26 ` Arnd Bergmann 2016-03-07 4:10 ` [PATCH 4/4] MAINTAINERS: add myself as ARM/LG1K maintainer Chanho Min 2016-03-07 4:29 ` [PATCH 0/4] ARM64:SoC add a new platform, LG Electronics's lg1k Arnd Bergmann 2016-03-07 6:45 ` Chanho Min
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