* [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters
@ 2016-01-29 8:29 Huang Rui
2016-01-29 8:29 ` [PATCH 1/2] perf/x86/msr: Add AMD performance time-stamp counter support Huang Rui
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Huang Rui @ 2016-01-29 8:29 UTC (permalink / raw)
To: Borislav Petkov, Peter Zijlstra, Ingo Molnar, Andy Lutomirski,
Thomas Gleixner, Robert Richter, Jacob Shin,
Arnaldo Carvalho de Melo, Kan Liang
Cc: linux-kernel, spg_linux_kernel, x86, Suravee Suthikulpanit,
Aravind Gopalakrishnan, Borislav Petkov, Fengguang Wu, Huang Rui
Hi all,
This serials of patches add two event counters that are PTSC
(performance time-stamp counter) and IRperf (instructions retired
count) for AMD new processors. They are incicated by
CPUID.8000_0001H:ECX[27] and CPUID.8000_0008H:EBX[1] separately.
Thanks,
Rui
Huang Rui (2):
perf/x86/msr: Add AMD performance time-stamp counter support
perf/x86/msr: Add AMD instructions retired performance counter
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/msr-index.h | 4 ++++
arch/x86/kernel/cpu/perf_event_msr.c | 36 ++++++++++++++++++++++++++----------
3 files changed, 32 insertions(+), 10 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/2] perf/x86/msr: Add AMD performance time-stamp counter support 2016-01-29 8:29 [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui @ 2016-01-29 8:29 ` Huang Rui 2016-03-31 9:22 ` [tip:perf/core] perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support tip-bot for Huang Rui 2016-01-29 8:29 ` [PATCH 2/2] perf/x86/msr: Add AMD instructions retired performance counter Huang Rui 2016-03-21 10:09 ` [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui 2 siblings, 1 reply; 8+ messages in thread From: Huang Rui @ 2016-01-29 8:29 UTC (permalink / raw) To: Borislav Petkov, Peter Zijlstra, Ingo Molnar, Andy Lutomirski, Thomas Gleixner, Robert Richter, Jacob Shin, Arnaldo Carvalho de Melo, Kan Liang Cc: linux-kernel, spg_linux_kernel, x86, Suravee Suthikulpanit, Aravind Gopalakrishnan, Borislav Petkov, Fengguang Wu, Huang Rui AMD Carrizo (Family 15h, Model 60h) introduces a time-stamp counter which indicated by CPUID.8000_0001H:ECX[27]. It increments at a 100 MHz rate in all P-states, and C states, S0, or S1. The frequency is about 100MHz. This counter will be used for calculate processor power and other parts. So add an interface into MSR PMU to get the PTSC counter value. Signed-off-by: Huang Rui <ray.huang@amd.com> --- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/perf_event_msr.c | 8 ++++++++ 3 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index f7ba9fb..1f9d682 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -176,6 +176,7 @@ #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ +#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b05402e..0e873e3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -321,6 +321,7 @@ #define MSR_F15H_PERF_CTR 0xc0010201 #define MSR_F15H_NB_PERF_CTL 0xc0010240 #define MSR_F15H_NB_PERF_CTR 0xc0010241 +#define MSR_F15H_PTSC 0xc0010280 #define MSR_F15H_IC_CFG 0xc0011021 /* Fam 10h MSRs */ diff --git a/arch/x86/kernel/cpu/perf_event_msr.c b/arch/x86/kernel/cpu/perf_event_msr.c index ec863b9..6f6772f 100644 --- a/arch/x86/kernel/cpu/perf_event_msr.c +++ b/arch/x86/kernel/cpu/perf_event_msr.c @@ -6,6 +6,7 @@ enum perf_msr_id { PERF_MSR_MPERF = 2, PERF_MSR_PPERF = 3, PERF_MSR_SMI = 4, + PERF_MSR_PTSC = 5, PERF_MSR_EVENT_MAX, }; @@ -15,6 +16,11 @@ static bool test_aperfmperf(int idx) return boot_cpu_has(X86_FEATURE_APERFMPERF); } +static bool test_ptsc(int idx) +{ + return boot_cpu_has(X86_FEATURE_PTSC); +} + static bool test_intel(int idx) { if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || @@ -74,6 +80,7 @@ PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); +PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); static struct perf_msr msr[] = { [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, @@ -81,6 +88,7 @@ static struct perf_msr msr[] = { [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, + [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, }, }; static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [tip:perf/core] perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support 2016-01-29 8:29 ` [PATCH 1/2] perf/x86/msr: Add AMD performance time-stamp counter support Huang Rui @ 2016-03-31 9:22 ` tip-bot for Huang Rui 0 siblings, 0 replies; 8+ messages in thread From: tip-bot for Huang Rui @ 2016-03-31 9:22 UTC (permalink / raw) To: linux-tip-commits Cc: bp, suravee.suthikulpanit, hpa, torvalds, ray.huang, eranian, rric, jacob.w.shin, acme, Aravind.Gopalakrishnan, alexander.shishkin, acme, kan.liang, bp, fengguang.wu, mingo, peterz, linux-kernel, luto, tglx, jolsa, vincent.weaver Commit-ID: 8a22426184774d7ced9c1d3aa4d95d34101fb3be Gitweb: http://git.kernel.org/tip/8a22426184774d7ced9c1d3aa4d95d34101fb3be Author: Huang Rui <ray.huang@amd.com> AuthorDate: Fri, 29 Jan 2016 16:29:56 +0800 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Thu, 31 Mar 2016 10:30:39 +0200 perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support AMD Carrizo (Family 15h, Model 60h) introduces a time-stamp counter which is indicated by CPUID.8000_0001H:ECX[27]. It increments at a 100 MHz rate in all P-states, and C states, S0, or S1. The frequency is about 100MHz. This counter will be used to calculate processor power and other parts. So add an interface into the MSR PMU to get the PTSC counter value. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Borislav Petkov <bp@suse.de> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Jacob Shin <jacob.w.shin@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <rric@kernel.org> Cc: Stephane Eranian <eranian@google.com> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1454056197-5893-2-git-send-email-ray.huang@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/msr.c | 8 ++++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 1 + 3 files changed, 10 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index ec863b9..6f6772f 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -6,6 +6,7 @@ enum perf_msr_id { PERF_MSR_MPERF = 2, PERF_MSR_PPERF = 3, PERF_MSR_SMI = 4, + PERF_MSR_PTSC = 5, PERF_MSR_EVENT_MAX, }; @@ -15,6 +16,11 @@ static bool test_aperfmperf(int idx) return boot_cpu_has(X86_FEATURE_APERFMPERF); } +static bool test_ptsc(int idx) +{ + return boot_cpu_has(X86_FEATURE_PTSC); +} + static bool test_intel(int idx) { if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || @@ -74,6 +80,7 @@ PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); +PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); static struct perf_msr msr[] = { [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, @@ -81,6 +88,7 @@ static struct perf_msr msr[] = { [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, + [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, }, }; static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 44ebd04..bdf9042 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -177,6 +177,7 @@ #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ +#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 984ab75..6e6a5cc 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -326,6 +326,7 @@ #define MSR_F15H_PERF_CTR 0xc0010201 #define MSR_F15H_NB_PERF_CTL 0xc0010240 #define MSR_F15H_NB_PERF_CTR 0xc0010241 +#define MSR_F15H_PTSC 0xc0010280 #define MSR_F15H_IC_CFG 0xc0011021 /* Fam 10h MSRs */ ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] perf/x86/msr: Add AMD instructions retired performance counter 2016-01-29 8:29 [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui 2016-01-29 8:29 ` [PATCH 1/2] perf/x86/msr: Add AMD performance time-stamp counter support Huang Rui @ 2016-01-29 8:29 ` Huang Rui 2016-03-31 9:22 ` [tip:perf/core] perf/x86/msr: Add AMD IRPERF (Instructions Retired) " tip-bot for Huang Rui 2016-03-21 10:09 ` [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui 2 siblings, 1 reply; 8+ messages in thread From: Huang Rui @ 2016-01-29 8:29 UTC (permalink / raw) To: Borislav Petkov, Peter Zijlstra, Ingo Molnar, Andy Lutomirski, Thomas Gleixner, Robert Richter, Jacob Shin, Arnaldo Carvalho de Melo, Kan Liang Cc: linux-kernel, spg_linux_kernel, x86, Suravee Suthikulpanit, Aravind Gopalakrishnan, Borislav Petkov, Fengguang Wu, Huang Rui AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which indicated by CPUID.8000_0008H:EBX[1]. And dedicated Instructions Retired register (MSR 0xC000_000E9) increments on once for every instruction retired. Signed-off-by: Huang Rui <ray.huang@amd.com> --- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kernel/cpu/perf_event_msr.c | 30 +++++++++++++++++++----------- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 1f9d682..a0ec7cc 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -259,6 +259,7 @@ /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ +#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ /* * BUG word(s) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0e873e3..982dcda 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -308,6 +308,9 @@ #define MSR_AMD64_IBSOPDATA4 0xc001103d #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ +/* Fam 17h MSRs */ +#define MSR_F17H_IRPERF 0xc00000e9 + /* Fam 16h MSRs */ #define MSR_F16H_L2I_PERF_CTL 0xc0010230 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 diff --git a/arch/x86/kernel/cpu/perf_event_msr.c b/arch/x86/kernel/cpu/perf_event_msr.c index 6f6772f..7111400 100644 --- a/arch/x86/kernel/cpu/perf_event_msr.c +++ b/arch/x86/kernel/cpu/perf_event_msr.c @@ -7,6 +7,7 @@ enum perf_msr_id { PERF_MSR_PPERF = 3, PERF_MSR_SMI = 4, PERF_MSR_PTSC = 5, + PERF_MSR_IRPERF = 6, PERF_MSR_EVENT_MAX, }; @@ -21,6 +22,11 @@ static bool test_ptsc(int idx) return boot_cpu_has(X86_FEATURE_PTSC); } +static bool test_irperf(int idx) +{ + return boot_cpu_has(X86_FEATURE_IRPERF); +} + static bool test_intel(int idx) { if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || @@ -75,20 +81,22 @@ struct perf_msr { bool (*test)(int idx); }; -PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); -PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); -PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); -PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); -PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); -PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); +PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); +PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); +PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); +PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); +PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); +PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); +PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06"); static struct perf_msr msr[] = { - [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, - [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, - [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, - [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, - [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, + [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, + [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, + [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, + [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, + [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, }, + [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, }, }; static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [tip:perf/core] perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter 2016-01-29 8:29 ` [PATCH 2/2] perf/x86/msr: Add AMD instructions retired performance counter Huang Rui @ 2016-03-31 9:22 ` tip-bot for Huang Rui 0 siblings, 0 replies; 8+ messages in thread From: tip-bot for Huang Rui @ 2016-03-31 9:22 UTC (permalink / raw) To: linux-tip-commits Cc: vincent.weaver, suravee.suthikulpanit, acme, jacob.w.shin, rric, bp, mingo, torvalds, linux-kernel, kan.liang, peterz, fengguang.wu, eranian, acme, hpa, ray.huang, luto, alexander.shishkin, Aravind.Gopalakrishnan, tglx, bp, jolsa Commit-ID: aaf248848db503927644d28e239bc399ed45959f Gitweb: http://git.kernel.org/tip/aaf248848db503927644d28e239bc399ed45959f Author: Huang Rui <ray.huang@amd.com> AuthorDate: Fri, 29 Jan 2016 16:29:57 +0800 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Thu, 31 Mar 2016 10:30:39 +0200 perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which is indicated by CPUID.8000_0008H:EBX[1]. A dedicated Instructions Retired MSR register (MSR 0xC000_000E9) increments once for every instruction retired. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Borislav Petkov <bp@suse.de> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Jacob Shin <jacob.w.shin@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <rric@kernel.org> Cc: Stephane Eranian <eranian@google.com> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1454056197-5893-3-git-send-email-ray.huang@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/msr.c | 30 +++++++++++++++++++----------- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 6f6772f..7111400 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -7,6 +7,7 @@ enum perf_msr_id { PERF_MSR_PPERF = 3, PERF_MSR_SMI = 4, PERF_MSR_PTSC = 5, + PERF_MSR_IRPERF = 6, PERF_MSR_EVENT_MAX, }; @@ -21,6 +22,11 @@ static bool test_ptsc(int idx) return boot_cpu_has(X86_FEATURE_PTSC); } +static bool test_irperf(int idx) +{ + return boot_cpu_has(X86_FEATURE_IRPERF); +} + static bool test_intel(int idx) { if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || @@ -75,20 +81,22 @@ struct perf_msr { bool (*test)(int idx); }; -PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); -PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); -PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); -PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); -PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); -PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); +PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); +PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); +PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); +PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); +PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); +PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); +PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06"); static struct perf_msr msr[] = { - [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, - [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, - [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, - [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, - [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, + [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, + [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, + [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, + [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, + [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, }, + [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, }, }; static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index bdf9042..dd448a9 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -251,6 +251,7 @@ /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ +#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6e6a5cc..e0e2f7d 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -313,6 +313,9 @@ #define MSR_AMD64_IBSOPDATA4 0xc001103d #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ +/* Fam 17h MSRs */ +#define MSR_F17H_IRPERF 0xc00000e9 + /* Fam 16h MSRs */ #define MSR_F16H_L2I_PERF_CTL 0xc0010230 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters 2016-01-29 8:29 [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui 2016-01-29 8:29 ` [PATCH 1/2] perf/x86/msr: Add AMD performance time-stamp counter support Huang Rui 2016-01-29 8:29 ` [PATCH 2/2] perf/x86/msr: Add AMD instructions retired performance counter Huang Rui @ 2016-03-21 10:09 ` Huang Rui 2016-03-21 10:31 ` Borislav Petkov 2 siblings, 1 reply; 8+ messages in thread From: Huang Rui @ 2016-03-21 10:09 UTC (permalink / raw) To: Borislav Petkov, Peter Zijlstra, Ingo Molnar, Andy Lutomirski, Thomas Gleixner, Robert Richter, Jacob Shin, Arnaldo Carvalho de Melo, Kan Liang Cc: linux-kernel, spg_linux_kernel, x86, Suravee Suthikulpanit, Aravind Gopalakrishnan, Borislav Petkov, Fengguang Wu On Fri, Jan 29, 2016 at 04:29:55PM +0800, Huang Rui wrote: > Hi all, > > This serials of patches add two event counters that are PTSC > (performance time-stamp counter) and IRperf (instructions retired > count) for AMD new processors. They are incicated by > CPUID.8000_0001H:ECX[27] and CPUID.8000_0008H:EBX[1] separately. > > Thanks, > Rui > > Huang Rui (2): > perf/x86/msr: Add AMD performance time-stamp counter support > perf/x86/msr: Add AMD instructions retired performance counter > > arch/x86/include/asm/cpufeature.h | 2 ++ > arch/x86/include/asm/msr-index.h | 4 ++++ > arch/x86/kernel/cpu/perf_event_msr.c | 36 ++++++++++++++++++++++++++---------- > 3 files changed, 32 insertions(+), 10 deletions(-) > Hi Ingo, Peter, Boris, Can you apply these two patches since I sent two months before. Need I rebase them? Thanks, Rui ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters 2016-03-21 10:09 ` [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui @ 2016-03-21 10:31 ` Borislav Petkov 2016-03-21 12:40 ` Peter Zijlstra 0 siblings, 1 reply; 8+ messages in thread From: Borislav Petkov @ 2016-03-21 10:31 UTC (permalink / raw) To: Huang Rui Cc: Peter Zijlstra, Ingo Molnar, Andy Lutomirski, Thomas Gleixner, Robert Richter, Jacob Shin, Arnaldo Carvalho de Melo, Kan Liang, linux-kernel, spg_linux_kernel, x86, Suravee Suthikulpanit, Aravind Gopalakrishnan, Fengguang Wu On Mon, Mar 21, 2016 at 06:09:31PM +0800, Huang Rui wrote: > Can you apply these two patches since I sent two months before. Need I > rebase them? Yes, please rebase and test them ontop of 4.6-rc1 once Linus releases it at the end of this/beginning of next week. Thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters 2016-03-21 10:31 ` Borislav Petkov @ 2016-03-21 12:40 ` Peter Zijlstra 0 siblings, 0 replies; 8+ messages in thread From: Peter Zijlstra @ 2016-03-21 12:40 UTC (permalink / raw) To: Borislav Petkov Cc: Huang Rui, Ingo Molnar, Andy Lutomirski, Thomas Gleixner, Robert Richter, Jacob Shin, Arnaldo Carvalho de Melo, Kan Liang, linux-kernel, spg_linux_kernel, x86, Suravee Suthikulpanit, Aravind Gopalakrishnan, Fengguang Wu On Mon, Mar 21, 2016 at 11:31:24AM +0100, Borislav Petkov wrote: > On Mon, Mar 21, 2016 at 06:09:31PM +0800, Huang Rui wrote: > > Can you apply these two patches since I sent two months before. Need I > > rebase them? > > Yes, please rebase and test them ontop of 4.6-rc1 once Linus releases it > at the end of this/beginning of next week. No need, I stomped on them and now they fit again. ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-03-31 9:23 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-01-29 8:29 [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui 2016-01-29 8:29 ` [PATCH 1/2] perf/x86/msr: Add AMD performance time-stamp counter support Huang Rui 2016-03-31 9:22 ` [tip:perf/core] perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support tip-bot for Huang Rui 2016-01-29 8:29 ` [PATCH 2/2] perf/x86/msr: Add AMD instructions retired performance counter Huang Rui 2016-03-31 9:22 ` [tip:perf/core] perf/x86/msr: Add AMD IRPERF (Instructions Retired) " tip-bot for Huang Rui 2016-03-21 10:09 ` [PATCH 0/2] perf/x86/msr: Add some new AMD performance event counters Huang Rui 2016-03-21 10:31 ` Borislav Petkov 2016-03-21 12:40 ` Peter Zijlstra
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