From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753848AbcC3OpM (ORCPT ); Wed, 30 Mar 2016 10:45:12 -0400 Received: from mga04.intel.com ([192.55.52.120]:29615 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751631AbcC3OpK (ORCPT ); Wed, 30 Mar 2016 10:45:10 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,416,1455004800"; d="scan'208";a="944521099" Date: Wed, 30 Mar 2016 17:45:03 +0300 From: Mika Westerberg To: Cristina Ciocan Cc: mathias.nyman@linux.intel.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, irina.tirdea@intel.com, octavian.purdila@intel.com Subject: Re: [PATCH v2 0/6] Add pinctrl support for Baytrail Message-ID: <20160330144503.GY2099@lahna.fi.intel.com> References: <1459171780-24856-1-git-send-email-cristina.ciocan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1459171780-24856-1-git-send-email-cristina.ciocan@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 28, 2016 at 04:29:34PM +0300, Cristina Ciocan wrote: > Add support for pin control (pin muxing and pin configuration) for Baytrail > platform. > > It follows the design in pinctrl-intel.c, but could not use the > implementation in pinctrl-intel since there were significant differences: > - gpio pin pads are not ordered > - per group functions: for setting a certain mode, there are groups > that need setting pins with different values; for instance, for > setting USB ULPI pins to GPIO function, pin 2 (GPIO_SUS1) needs > to be set to function 1, wihle all other from the group need to be > set to 0 > - communities only need pin base and count as specific data > - irq set type only clears all flags, while the actual type setting > is made in the byt_irq_unmask function, which does not comply with > the intel pinctrl implementation > > Changes from v1: > - fix reg, reg_val and byt_soc_data not used variables warnings > > Cristina Ciocan (6): > pinctrl: baytrail: Add pin control data structures > pinctrl: baytrail: Add pin control operations > pinctrl: baytrail: Update gpio chip operations > pinctrl: baytrail: Update irq chip operations > pinctrl: baytrail: Register pin control handling > pinctrl: baytrail: Add debounce configuration Apart of the pin naming I commented, this patch series finally brings real pinctrl support to the misnamed baytrail GPIO driver which is definitely the right thing to do :) Acked-by: Mika Westerberg