From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758710AbcDHQAm (ORCPT ); Fri, 8 Apr 2016 12:00:42 -0400 Received: from muru.com ([72.249.23.125]:50135 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753454AbcDHQAk (ORCPT ); Fri, 8 Apr 2016 12:00:40 -0400 Date: Fri, 8 Apr 2016 09:00:34 -0700 From: Tony Lindgren To: Keerthy Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, lokeshvutla@ti.com, t-kristo@ti.com, linux-omap@vger.kernel.org Subject: Re: [PATCH v3] ARM: dts: dra7: Correct clock tree for sys_32k_ck Message-ID: <20160408160033.GV16484@atomide.com> References: <1459748235-27232-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1459748235-27232-1-git-send-email-j-keerthy@ti.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Keerthy [160403 22:38]: > This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source. > Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external > crystal is not enabled at power up. Instead the CPU falls back to using > an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually > 20MHz on boards so far (which gives an emulated frequency of 32.786KHz) > > Modelling the same in device tree. > > Acked-by: Tero Kristo > Signed-off-by: Keerthy > Signed-off-by: Lokesh Vutla > --- > Errata Document: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf > Errata number: i856 > > Tested the debugfs clock tree nodes on DRA7-EVM. > > Changes in v3: > > Rebased to 4.6-rc2 > Tested on top of omap-for-v4.6/fixes-rc1 branch and the patch applied > cleanly. Thanks applying into omap-for-v4.6/fixes. Tony