[PATCH 01/12] mtd: nand: bf5xx: set ECC algorithm explicitly

[PATCH 01/12] mtd: nand: bf5xx: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/bf5xx_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index b38f414..37da423 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -817,6 +817,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev)
 		chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
 	} else {
 		chip->ecc.mode	    = NAND_ECC_SOFT;
+		chip->ecc.algo	= NAND_ECC_HAMMING;
 	}
 
 	/* scan hardware nand chip and setup mtd info data struct */
-- 
1.8.4.5

[PATCH 02/12] mtd: nand: davinci: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 drivers/mtd/nand/davinci_nand.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index fe3fd29..b0a2801 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -738,6 +738,14 @@ static int nand_davinci_probe(struct platform_device *pdev)
 	}
 	info->chip.ecc.mode = ecc_mode;
 
+	/*
+	 * When using software ECC this driver support hamming only. Force
+	 * ecc.algo to NAND_ECC_HAMMING to avoid adding an extra ->ecc_algo
+	 * field to davinci_nand_pdata.
+	 */
+	if (ecc_mode == NAND_ECC_SOFT)
+		info->chip.ecc.algo = NAND_ECC_HAMMING;
+
 	info->clk = devm_clk_get(&pdev->dev, "aemif");
 	if (IS_ERR(info->clk)) {
 		ret = PTR_ERR(info->clk);
-- 
1.8.4.5

[PATCH 03/12] avr32: set Atmel NAND ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 arch/avr32/boards/atngw100/setup.c      | 1 +
 arch/avr32/boards/atstk1000/atstk1002.c | 1 +
 include/linux/platform_data/atmel.h     | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index afeae89..b059b97 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -98,6 +98,7 @@ static struct atmel_nand_data atngw100mkii_nand_data __initdata = {
 	.enable_pin	= GPIO_PIN_PE(23),
 	.bus_width_16	= true,
 	.ecc_mode	= NAND_ECC_SOFT,
+	.ecc_algo	= NAND_ECC_HAMMING,
 	.parts		= nand_partitions,
 	.num_parts	= ARRAY_SIZE(nand_partitions),
 };
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index 6c80aba..6b45faf 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -96,6 +96,7 @@ static struct atmel_nand_data atstk1006_nand_data __initdata = {
 	.rdy_pin	= GPIO_PIN_PB(30),
 	.enable_pin	= GPIO_PIN_PB(29),
 	.ecc_mode	= NAND_ECC_SOFT,
+	.ecc_algo	= NAND_ECC_HAMMING,
 	.parts		= nand_partitions,
 	.num_parts	= ARRAY_SIZE(nand_partitions),
 };
diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
index 3c8825b..a283b3d 100644
--- a/include/linux/platform_data/atmel.h
+++ b/include/linux/platform_data/atmel.h
@@ -33,6 +33,7 @@ struct atmel_nand_data {
 	u8		cle;			/* address line number connected to CLE */
 	u8		bus_width_16;		/* buswidth is 16 bit */
 	u8		ecc_mode;		/* ecc mode */
+	enum nand_ecc_algo ecc_algo;		/* ecc algorithm */
 	u8		on_flash_bbt;		/* bbt on flash */
 	struct mtd_partition *parts;
 	unsigned int	num_parts;
-- 
1.8.4.5

Re: [PATCH 03/12] avr32: set Atmel NAND ECC algorithm explicitly

[Boris Brezillon]

On Fri, 15 Apr 2016 21:54:03 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).

Not sure we really need to add this ->ecc_algo field: none of the
existing AVR32 boards use software BCH implementation, and I don't
expect to see new AVR32 boards :-). How about setting NAND_ECC_HAMMING
when ecc_mode == NAND_ECC_SOFT directly in the atmel_nand driver?

> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  arch/avr32/boards/atngw100/setup.c      | 1 +
>  arch/avr32/boards/atstk1000/atstk1002.c | 1 +
>  include/linux/platform_data/atmel.h     | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
> index afeae89..b059b97 100644
> --- a/arch/avr32/boards/atngw100/setup.c
> +++ b/arch/avr32/boards/atngw100/setup.c
> @@ -98,6 +98,7 @@ static struct atmel_nand_data atngw100mkii_nand_data __initdata = {
>  	.enable_pin	= GPIO_PIN_PE(23),
>  	.bus_width_16	= true,
>  	.ecc_mode	= NAND_ECC_SOFT,
> +	.ecc_algo	= NAND_ECC_HAMMING,
>  	.parts		= nand_partitions,
>  	.num_parts	= ARRAY_SIZE(nand_partitions),
>  };
> diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
> index 6c80aba..6b45faf 100644
> --- a/arch/avr32/boards/atstk1000/atstk1002.c
> +++ b/arch/avr32/boards/atstk1000/atstk1002.c
> @@ -96,6 +96,7 @@ static struct atmel_nand_data atstk1006_nand_data __initdata = {
>  	.rdy_pin	= GPIO_PIN_PB(30),
>  	.enable_pin	= GPIO_PIN_PB(29),
>  	.ecc_mode	= NAND_ECC_SOFT,
> +	.ecc_algo	= NAND_ECC_HAMMING,
>  	.parts		= nand_partitions,
>  	.num_parts	= ARRAY_SIZE(nand_partitions),
>  };
> diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
> index 3c8825b..a283b3d 100644
> --- a/include/linux/platform_data/atmel.h
> +++ b/include/linux/platform_data/atmel.h
> @@ -33,6 +33,7 @@ struct atmel_nand_data {
>  	u8		cle;			/* address line number connected to CLE */
>  	u8		bus_width_16;		/* buswidth is 16 bit */
>  	u8		ecc_mode;		/* ecc mode */
> +	enum nand_ecc_algo ecc_algo;		/* ecc algorithm */
>  	u8		on_flash_bbt;		/* bbt on flash */
>  	struct mtd_partition *parts;
>  	unsigned int	num_parts;



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 03/12] avr32: set Atmel NAND ECC algorithm explicitly

[Hans-Christian Noren Egtvedt]

Around Fri 15 Apr 2016 21:54:03 +0200 or thereabout, Rafał Miłecki wrote:
> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

Acked-by: Hans-Christian Noren Egtvedt <egtvedt@samfundet.no>

> ---
>  arch/avr32/boards/atngw100/setup.c      | 1 +
>  arch/avr32/boards/atstk1000/atstk1002.c | 1 +
>  include/linux/platform_data/atmel.h     | 1 +
>  3 files changed, 3 insertions(+)

<snipp diff>

-- 
Best regards, HcE.

[PATCH 04/12] mtd: nand: atmel: set ECC algorithm explicitly

[Rafał Miłecki]

Set it to value obtained from platform data with fallback to Hamming.
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/atmel_nand.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index eec8ca7..6aa82e4 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1212,6 +1212,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		dev_warn(host->dev,
 			"Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1295,6 +1296,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1613,6 +1615,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * even if the nand-ecc-mode property is not defined.
 	 */
 	host->nand_chip.ecc.mode = NAND_ECC_SOFT;
+	host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
 
 	return 0;
 }
@@ -1629,6 +1632,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
 		dev_err(host->dev,
 			"Can't get I/O resource regs, use software ECC\n");
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1661,6 +1665,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -2159,6 +2164,7 @@ static int atmel_nand_probe(struct platform_device *pdev)
 		memcpy(&host->board, dev_get_platdata(&pdev->dev),
 		       sizeof(struct atmel_nand_data));
 		nand_chip->ecc.mode = host->board.ecc_mode;
+		nand_chip->ecc.algo = host->board.ecc_algo;
 
 		/* 16-bit bus width */
 		if (host->board.bus_width_16)
-- 
1.8.4.5

Re: [PATCH 04/12] mtd: nand: atmel: set ECC algorithm explicitly

[Boris Brezillon]

On Fri, 15 Apr 2016 21:54:04 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> Set it to value obtained from platform data with fallback to Hamming.
> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/mtd/nand/atmel_nand.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index eec8ca7..6aa82e4 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -1212,6 +1212,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
>  		dev_warn(host->dev,
>  			"Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
>  		nand_chip->ecc.mode = NAND_ECC_SOFT;
> +		nand_chip->ecc.algo = NAND_ECC_HAMMING;
>  		return 0;
>  	}
>  
> @@ -1295,6 +1296,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
>  		/* page size not handled by HW ECC */
>  		/* switching back to soft ECC */
>  		nand_chip->ecc.mode = NAND_ECC_SOFT;
> +		nand_chip->ecc.algo = NAND_ECC_HAMMING;
>  		return 0;
>  	}
>  
> @@ -1613,6 +1615,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
>  	 * even if the nand-ecc-mode property is not defined.
>  	 */
>  	host->nand_chip.ecc.mode = NAND_ECC_SOFT;
> +	host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
>  
>  	return 0;
>  }
> @@ -1629,6 +1632,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
>  		dev_err(host->dev,
>  			"Can't get I/O resource regs, use software ECC\n");
>  		nand_chip->ecc.mode = NAND_ECC_SOFT;
> +		nand_chip->ecc.algo = NAND_ECC_HAMMING;
>  		return 0;
>  	}
>  
> @@ -1661,6 +1665,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
>  		/* page size not handled by HW ECC */
>  		/* switching back to soft ECC */
>  		nand_chip->ecc.mode = NAND_ECC_SOFT;
> +		nand_chip->ecc.algo = NAND_ECC_HAMMING;
>  		return 0;
>  	}
>  
> @@ -2159,6 +2164,7 @@ static int atmel_nand_probe(struct platform_device *pdev)
>  		memcpy(&host->board, dev_get_platdata(&pdev->dev),
>  		       sizeof(struct atmel_nand_data));
>  		nand_chip->ecc.mode = host->board.ecc_mode;
> +		nand_chip->ecc.algo = host->board.ecc_algo;

If you follow my suggestion on patch 3, it should be:

		if (host->board.ecc_mode == NAND_ECC_SOFT)
			nand_chip->ecc.algo = NAND_ECC_HAMMING;

This way we avoid any dependency between the avr32 and nand tree.

>  
>  		/* 16-bit bus width */
>  		if (host->board.bus_width_16)



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 05/12] CRIS v32: nand: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 1 +
 arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
index 5aa3f51..3f646c7 100644
--- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
@@ -157,6 +157,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
 	/* 20 us command delay time */
 	this->chip_delay = 20;
 	this->ecc.mode = NAND_ECC_SOFT;
+	this->ecc.algo = NAND_ECC_HAMMING;
 
 	/* Enable the following for a flash based bad block table */
 	/* this->bbt_options = NAND_BBT_USE_FLASH; */
diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
index a7c17b0..a745405 100644
--- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
@@ -148,6 +148,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
 	/* 20 us command delay time */
 	this->chip_delay = 20;
 	this->ecc.mode = NAND_ECC_SOFT;
+	this->ecc.algo = NAND_ECC_HAMMING;
 
 	/* Enable the following for a flash based bad block table */
 	/* this->bbt_options = NAND_BBT_USE_FLASH; */
-- 
1.8.4.5

[PATCH 06/12] staging: mt29f_spinand: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/staging/mt29f_spinand/mt29f_spinand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/mt29f_spinand/mt29f_spinand.c b/drivers/staging/mt29f_spinand/mt29f_spinand.c
index f503699..e389009 100644
--- a/drivers/staging/mt29f_spinand/mt29f_spinand.c
+++ b/drivers/staging/mt29f_spinand/mt29f_spinand.c
@@ -900,6 +900,7 @@ static int spinand_probe(struct spi_device *spi_nand)
 	chip->ecc.write_page = spinand_write_page_hwecc;
 #else
 	chip->ecc.mode	= NAND_ECC_SOFT;
+	chip->ecc.algo	= NAND_ECC_HAMMING;
 	if (spinand_disable_ecc(spi_nand) < 0)
 		dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
 			 __func__);
-- 
1.8.4.5

[PATCH 07/12] mtd: nand: set ECC algorithm to Hamming on fallback

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/nand_base.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dd02c09..e1f3cf8 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4245,6 +4245,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 		pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
 			ecc->size, mtd->writesize);
 		ecc->mode = NAND_ECC_SOFT;
+		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
 		ecc->calculate = nand_calculate_ecc;
-- 
1.8.4.5

[PATCH 08/12] mtd: nand: hisi504: set ECC algorithm based on DT info

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/hisi504_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c
index 7bf844c..f917297 100644
--- a/drivers/mtd/nand/hisi504_nand.c
+++ b/drivers/mtd/nand/hisi504_nand.c
@@ -768,6 +768,7 @@ static int hisi_nfc_probe(struct platform_device *pdev)
 	chip->chip_delay	= HINFC504_CHIP_DELAY;
 
 	chip->ecc.mode = of_get_nand_ecc_mode(np);
+	chip->ecc.algo = of_get_nand_ecc_algo(np);
 
 	buswidth = of_get_nand_bus_width(np);
 	if (buswidth == 16)
-- 
1.8.4.5

Re: [PATCH 08/12] mtd: nand: hisi504: set ECC algorithm based on DT info

[Boris Brezillon]

On Fri, 15 Apr 2016 21:54:08 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/mtd/nand/hisi504_nand.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c
> index 7bf844c..f917297 100644
> --- a/drivers/mtd/nand/hisi504_nand.c
> +++ b/drivers/mtd/nand/hisi504_nand.c
> @@ -768,6 +768,7 @@ static int hisi_nfc_probe(struct platform_device *pdev)
>  	chip->chip_delay	= HINFC504_CHIP_DELAY;
>  
>  	chip->ecc.mode = of_get_nand_ecc_mode(np);
> +	chip->ecc.algo = of_get_nand_ecc_algo(np);

I'm trying to remove those explicit ecc.xxx = of_get_nand_xxx()
assignments and rely on the initialization done in nand_scan_ident()
(see this series [1]).
I'd like to apply the remaining patches in [1] before this series, which
means this patch will be useless. No need to resend the series though,
I'll skip this patch while applying, just wanted to let you know.

>  
>  	buswidth = of_get_nand_bus_width(np);
>  	if (buswidth == 16)

[1]http://lkml.iu.edu/hypermail/linux/kernel/1604.0/00298.html

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 09/12] mtd: nand: fsmc: validate ECC setup by checking algorithm directly

[Rafał Miłecki]

NAND core sets ECC algorithm in algo field now and it should be
preferred over the mode field. This also prepares driver for dropping
NAND_ECC_SOFT_BCH.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 1372040..0f8c63f 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -958,9 +958,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			nand->ecc.strength = 1;
 			break;
 
+		case NAND_ECC_SOFT:
 		case NAND_ECC_SOFT_BCH:
-			dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
-			break;
+			if (nand->ecc.algo == NAND_ECC_BCH) {
+				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
+				break;
+			}
 
 		default:
 			dev_err(&pdev->dev, "Unsupported ECC mode!\n");
-- 
1.8.4.5

Re: [PATCH 09/12] mtd: nand: fsmc: validate ECC setup by checking algorithm directly

[Joe Perches]

On Fri, 2016-04-15 at 21:54 +0200, Rafał Miłecki wrote:
> NAND core sets ECC algorithm in algo field now and it should be
> preferred over the mode field. This also prepares driver for dropping
> NAND_ECC_SOFT_BCH.
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/mtd/nand/fsmc_nand.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 1372040..0f8c63f 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -958,9 +958,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>  			nand->ecc.strength = 1;
>  			break;
>  
> +		case NAND_ECC_SOFT:
>  		case NAND_ECC_SOFT_BCH:
> -			dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
> -			break;
> +			if (nand->ecc.algo == NAND_ECC_BCH) {
> +				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
> +				break;
> +			}
>  
>  		default:
>  			dev_err(&pdev->dev, "Unsupported ECC mode!\n");

Why not just add NAND_ECC_SOFT above the default case?

Re: [PATCH 09/12] mtd: nand: fsmc: validate ECC setup by checking algorithm directly

[Joe Perches]

On Fri, 2016-04-15 at 13:23 -0700, Joe Perches wrote:
> Why not just add NAND_ECC_SOFT above the default case?

Nevermind, misread.

Re: [PATCH 09/12] mtd: nand: fsmc: validate ECC setup by checking algorithm directly

[Rafał Miłecki]

On 15 April 2016 at 22:24, Joe Perches <joe@perches.com> wrote:
> On Fri, 2016-04-15 at 13:23 -0700, Joe Perches wrote:
>> Why not just add NAND_ECC_SOFT above the default case?
>
> Nevermind, misread.

At least someone reviews it which is nice :)

-- 
Rafał

[PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Rafał Miłecki]

Now we have all drivers properly setting this new field we can start
using it and proceed with deprecating NAND_ECC_SOFT_BCH.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
 1 file changed, 53 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index e1f3cf8..ffd1b32 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4154,7 +4154,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 	/*
 	 * If no default placement scheme is given, select an appropriate one.
 	 */
-	if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
+	if (!mtd->ooblayout && ecc->algo != NAND_ECC_BCH) {
 		switch (mtd->oobsize) {
 		case 8:
 		case 16:
@@ -4248,51 +4248,59 @@ int nand_scan_tail(struct mtd_info *mtd)
 		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
-		ecc->calculate = nand_calculate_ecc;
-		ecc->correct = nand_correct_data;
-		ecc->read_page = nand_read_page_swecc;
-		ecc->read_subpage = nand_read_subpage;
-		ecc->write_page = nand_write_page_swecc;
-		ecc->read_page_raw = nand_read_page_raw;
-		ecc->write_page_raw = nand_write_page_raw;
-		ecc->read_oob = nand_read_oob_std;
-		ecc->write_oob = nand_write_oob_std;
-		if (!ecc->size)
-			ecc->size = 256;
-		ecc->bytes = 3;
-		ecc->strength = 1;
-		break;
-
 	case NAND_ECC_SOFT_BCH:
-		if (!mtd_nand_has_bch()) {
-			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
-			ret = -EINVAL;
-			goto err_free;
-		}
-		ecc->calculate = nand_bch_calculate_ecc;
-		ecc->correct = nand_bch_correct_data;
-		ecc->read_page = nand_read_page_swecc;
-		ecc->read_subpage = nand_read_subpage;
-		ecc->write_page = nand_write_page_swecc;
-		ecc->read_page_raw = nand_read_page_raw;
-		ecc->write_page_raw = nand_write_page_raw;
-		ecc->read_oob = nand_read_oob_std;
-		ecc->write_oob = nand_write_oob_std;
-		/*
-		 * Board driver should supply ecc.size and ecc.strength values
-		 * to select how many bits are correctable. Otherwise, default
-		 * to 4 bits for large page devices.
-		 */
-		if (!ecc->size && (mtd->oobsize >= 64)) {
-			ecc->size = 512;
-			ecc->strength = 4;
-		}
+		switch (ecc->algo) {
+		case NAND_ECC_HAMMING:
+			ecc->calculate = nand_calculate_ecc;
+			ecc->correct = nand_correct_data;
+			ecc->read_page = nand_read_page_swecc;
+			ecc->read_subpage = nand_read_subpage;
+			ecc->write_page = nand_write_page_swecc;
+			ecc->read_page_raw = nand_read_page_raw;
+			ecc->write_page_raw = nand_write_page_raw;
+			ecc->read_oob = nand_read_oob_std;
+			ecc->write_oob = nand_write_oob_std;
+			if (!ecc->size)
+				ecc->size = 256;
+			ecc->bytes = 3;
+			ecc->strength = 1;
+			break;
+		case NAND_ECC_BCH:
+			if (!mtd_nand_has_bch()) {
+				WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
+				ret = -EINVAL;
+				goto err_free;
+			}
+			ecc->calculate = nand_bch_calculate_ecc;
+			ecc->correct = nand_bch_correct_data;
+			ecc->read_page = nand_read_page_swecc;
+			ecc->read_subpage = nand_read_subpage;
+			ecc->write_page = nand_write_page_swecc;
+			ecc->read_page_raw = nand_read_page_raw;
+			ecc->write_page_raw = nand_write_page_raw;
+			ecc->read_oob = nand_read_oob_std;
+			ecc->write_oob = nand_write_oob_std;
+			/*
+			* Board driver should supply ecc.size and ecc.strength
+			* values to select how many bits are correctable.
+			* Otherwise, default to 4 bits for large page devices.
+			*/
+			if (!ecc->size && (mtd->oobsize >= 64)) {
+				ecc->size = 512;
+				ecc->strength = 4;
+			}
 
-		/* See nand_bch_init() for details. */
-		ecc->bytes = 0;
-		ecc->priv = nand_bch_init(mtd);
-		if (!ecc->priv) {
-			WARN(1, "BCH ECC initialization failed!\n");
+			/* See nand_bch_init() for details. */
+			ecc->bytes = 0;
+			ecc->priv = nand_bch_init(mtd);
+			if (!ecc->priv) {
+				WARN(1, "BCH ECC initialization failed!\n");
+				ret = -EINVAL;
+				goto err_free;
+			}
+			break;
+		default:
+			WARN(1, "Unsupported ECC algorithm!\n");
 			ret = -EINVAL;
 			goto err_free;
 		}
@@ -4478,7 +4486,7 @@ void nand_release(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
-	if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
+	if (chip->ecc.algo == NAND_ECC_BCH)
 		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
 
 	mtd_device_unregister(mtd);
-- 
1.8.4.5

Re: [PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Boris Brezillon]

On Fri, 15 Apr 2016 21:54:10 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> Now we have all drivers properly setting this new field we can start
> using it and proceed with deprecating NAND_ECC_SOFT_BCH.
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
>  1 file changed, 53 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index e1f3cf8..ffd1b32 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -4154,7 +4154,7 @@ int nand_scan_tail(struct mtd_info *mtd)
>  	/*
>  	 * If no default placement scheme is given, select an appropriate one.
>  	 */
> -	if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
> +	if (!mtd->ooblayout && ecc->algo != NAND_ECC_BCH) {

Should be:

	if (!mtd->ooblayout && ecc->algo == NAND_ECC_SOFT &&
	    ecc->algo != NAND_ECC_BCH) {

Otherwise you're also taking the NAND_ECC_HW + NAND_ECC_BCH into
account. 

>  		switch (mtd->oobsize) {
>  		case 8:
>  		case 16:
> @@ -4248,51 +4248,59 @@ int nand_scan_tail(struct mtd_info *mtd)
>  		ecc->algo = NAND_ECC_HAMMING;
>  
>  	case NAND_ECC_SOFT:
> -		ecc->calculate = nand_calculate_ecc;
> -		ecc->correct = nand_correct_data;
> -		ecc->read_page = nand_read_page_swecc;
> -		ecc->read_subpage = nand_read_subpage;
> -		ecc->write_page = nand_write_page_swecc;
> -		ecc->read_page_raw = nand_read_page_raw;
> -		ecc->write_page_raw = nand_write_page_raw;
> -		ecc->read_oob = nand_read_oob_std;
> -		ecc->write_oob = nand_write_oob_std;
> -		if (!ecc->size)
> -			ecc->size = 256;
> -		ecc->bytes = 3;
> -		ecc->strength = 1;
> -		break;
> -
>  	case NAND_ECC_SOFT_BCH:

Shouldn't we drop this case?

> -		if (!mtd_nand_has_bch()) {
> -			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
> -			ret = -EINVAL;
> -			goto err_free;
> -		}
> -		ecc->calculate = nand_bch_calculate_ecc;
> -		ecc->correct = nand_bch_correct_data;
> -		ecc->read_page = nand_read_page_swecc;
> -		ecc->read_subpage = nand_read_subpage;
> -		ecc->write_page = nand_write_page_swecc;
> -		ecc->read_page_raw = nand_read_page_raw;
> -		ecc->write_page_raw = nand_write_page_raw;
> -		ecc->read_oob = nand_read_oob_std;
> -		ecc->write_oob = nand_write_oob_std;
> -		/*
> -		 * Board driver should supply ecc.size and ecc.strength values
> -		 * to select how many bits are correctable. Otherwise, default
> -		 * to 4 bits for large page devices.
> -		 */
> -		if (!ecc->size && (mtd->oobsize >= 64)) {
> -			ecc->size = 512;
> -			ecc->strength = 4;
> -		}
> +		switch (ecc->algo) {

Please put this logic in a sub-function, nand_scan_tail() is already
quite long and hard to read, let's try to not define sub switch-case
blocks inside existing ones.

> +		case NAND_ECC_HAMMING:
> +			ecc->calculate = nand_calculate_ecc;
> +			ecc->correct = nand_correct_data;
> +			ecc->read_page = nand_read_page_swecc;
> +			ecc->read_subpage = nand_read_subpage;
> +			ecc->write_page = nand_write_page_swecc;
> +			ecc->read_page_raw = nand_read_page_raw;
> +			ecc->write_page_raw = nand_write_page_raw;
> +			ecc->read_oob = nand_read_oob_std;
> +			ecc->write_oob = nand_write_oob_std;
> +			if (!ecc->size)
> +				ecc->size = 256;
> +			ecc->bytes = 3;
> +			ecc->strength = 1;
> +			break;
> +		case NAND_ECC_BCH:
> +			if (!mtd_nand_has_bch()) {
> +				WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
> +				ret = -EINVAL;
> +				goto err_free;
> +			}
> +			ecc->calculate = nand_bch_calculate_ecc;
> +			ecc->correct = nand_bch_correct_data;
> +			ecc->read_page = nand_read_page_swecc;
> +			ecc->read_subpage = nand_read_subpage;
> +			ecc->write_page = nand_write_page_swecc;
> +			ecc->read_page_raw = nand_read_page_raw;
> +			ecc->write_page_raw = nand_write_page_raw;
> +			ecc->read_oob = nand_read_oob_std;
> +			ecc->write_oob = nand_write_oob_std;
> +			/*
> +			* Board driver should supply ecc.size and ecc.strength
> +			* values to select how many bits are correctable.
> +			* Otherwise, default to 4 bits for large page devices.
> +			*/
> +			if (!ecc->size && (mtd->oobsize >= 64)) {
> +				ecc->size = 512;
> +				ecc->strength = 4;
> +			}
>  
> -		/* See nand_bch_init() for details. */
> -		ecc->bytes = 0;
> -		ecc->priv = nand_bch_init(mtd);
> -		if (!ecc->priv) {
> -			WARN(1, "BCH ECC initialization failed!\n");
> +			/* See nand_bch_init() for details. */
> +			ecc->bytes = 0;
> +			ecc->priv = nand_bch_init(mtd);
> +			if (!ecc->priv) {
> +				WARN(1, "BCH ECC initialization failed!\n");
> +				ret = -EINVAL;
> +				goto err_free;
> +			}
> +			break;
> +		default:
> +			WARN(1, "Unsupported ECC algorithm!\n");
>  			ret = -EINVAL;
>  			goto err_free;
>  		}
> @@ -4478,7 +4486,7 @@ void nand_release(struct mtd_info *mtd)
>  {
>  	struct nand_chip *chip = mtd_to_nand(mtd);
>  
> -	if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
> +	if (chip->ecc.algo == NAND_ECC_BCH)

Again, should be:

	if (chip->ecc.mode = NAND_ECC_SOFT &&
	    chip->ecc.algo == NAND_ECC_BCH)

>  		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
>  
>  	mtd_device_unregister(mtd);



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Boris Brezillon]

On Sat, 16 Apr 2016 09:58:07 +0200
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:

> On Fri, 15 Apr 2016 21:54:10 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
> 
> > Now we have all drivers properly setting this new field we can start
> > using it and proceed with deprecating NAND_ECC_SOFT_BCH.
> > 
> > Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> > ---
> >  drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
> >  1 file changed, 53 insertions(+), 45 deletions(-)
> > 

[...]

> > @@ -4248,51 +4248,59 @@ int nand_scan_tail(struct mtd_info *mtd)
> >  		ecc->algo = NAND_ECC_HAMMING;
> >  
> >  	case NAND_ECC_SOFT:
> > -		ecc->calculate = nand_calculate_ecc;
> > -		ecc->correct = nand_correct_data;
> > -		ecc->read_page = nand_read_page_swecc;
> > -		ecc->read_subpage = nand_read_subpage;
> > -		ecc->write_page = nand_write_page_swecc;
> > -		ecc->read_page_raw = nand_read_page_raw;
> > -		ecc->write_page_raw = nand_write_page_raw;
> > -		ecc->read_oob = nand_read_oob_std;
> > -		ecc->write_oob = nand_write_oob_std;
> > -		if (!ecc->size)
> > -			ecc->size = 256;
> > -		ecc->bytes = 3;
> > -		ecc->strength = 1;
> > -		break;
> > -
> >  	case NAND_ECC_SOFT_BCH:
> 
> Shouldn't we drop this case?

Nevermind, I see you're dropping it in the last patch.


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Rafał Miłecki]

On 16 April 2016 at 09:58, Boris Brezillon
<boris.brezillon@free-electrons.com> wrote:
> On Fri, 15 Apr 2016 21:54:10 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
>
>> Now we have all drivers properly setting this new field we can start
>> using it and proceed with deprecating NAND_ECC_SOFT_BCH.
>>
>> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
>> ---
>>  drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
>>  1 file changed, 53 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
>> index e1f3cf8..ffd1b32 100644
>> --- a/drivers/mtd/nand/nand_base.c
>> +++ b/drivers/mtd/nand/nand_base.c
>> @@ -4154,7 +4154,7 @@ int nand_scan_tail(struct mtd_info *mtd)
>>       /*
>>        * If no default placement scheme is given, select an appropriate one.
>>        */
>> -     if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
>> +     if (!mtd->ooblayout && ecc->algo != NAND_ECC_BCH) {
>
> Should be:
>
>         if (!mtd->ooblayout && ecc->algo == NAND_ECC_SOFT &&
>             ecc->algo != NAND_ECC_BCH) {
>
> Otherwise you're also taking the NAND_ECC_HW + NAND_ECC_BCH into
> account.

Pretty much yes, but without
[PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
we may be getting NAND_ECC_SOFT as well as NAND_ECC_SOFT_BCH. And
11/12 can't be applied before 10/12. We'll need to support both values
for this very short moment (after 10/12 but before 11/12).

Re: [PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Boris Brezillon]

On Sun, 17 Apr 2016 18:27:40 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> On 16 April 2016 at 09:58, Boris Brezillon
> <boris.brezillon@free-electrons.com> wrote:
> > On Fri, 15 Apr 2016 21:54:10 +0200
> > Rafał Miłecki <zajec5@gmail.com> wrote:
> >
> >> Now we have all drivers properly setting this new field we can start
> >> using it and proceed with deprecating NAND_ECC_SOFT_BCH.
> >>
> >> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> >> ---
> >>  drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
> >>  1 file changed, 53 insertions(+), 45 deletions(-)
> >>
> >> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> >> index e1f3cf8..ffd1b32 100644
> >> --- a/drivers/mtd/nand/nand_base.c
> >> +++ b/drivers/mtd/nand/nand_base.c
> >> @@ -4154,7 +4154,7 @@ int nand_scan_tail(struct mtd_info *mtd)
> >>       /*
> >>        * If no default placement scheme is given, select an appropriate one.
> >>        */
> >> -     if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
> >> +     if (!mtd->ooblayout && ecc->algo != NAND_ECC_BCH) {
> >
> > Should be:
> >
> >         if (!mtd->ooblayout && ecc->algo == NAND_ECC_SOFT &&
> >             ecc->algo != NAND_ECC_BCH) {
> >
> > Otherwise you're also taking the NAND_ECC_HW + NAND_ECC_BCH into
> > account.
> 
> Pretty much yes, but without
> [PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
> we may be getting NAND_ECC_SOFT as well as NAND_ECC_SOFT_BCH. And
> 11/12 can't be applied before 10/12. We'll need to support both values
> for this very short moment (after 10/12 but before 11/12).


Why can't you move patch 11 before patch 10. The DT parsing code has
already been patched to set both ecc->algo to NAND_ECC_BCH and
ecc->mode to NAND_ECC_SOFT, so, to it seems perfectly safe to reorder
those changes to me (and change the test as suggested).

Am I missing something?

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Boris Brezillon]

On Sun, 17 Apr 2016 18:50:05 +0200
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:

> On Sun, 17 Apr 2016 18:27:40 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
> 
> > On 16 April 2016 at 09:58, Boris Brezillon
> > <boris.brezillon@free-electrons.com> wrote:
> > > On Fri, 15 Apr 2016 21:54:10 +0200
> > > Rafał Miłecki <zajec5@gmail.com> wrote:
> > >
> > >> Now we have all drivers properly setting this new field we can start
> > >> using it and proceed with deprecating NAND_ECC_SOFT_BCH.
> > >>
> > >> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> > >> ---
> > >>  drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
> > >>  1 file changed, 53 insertions(+), 45 deletions(-)
> > >>
> > >> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> > >> index e1f3cf8..ffd1b32 100644
> > >> --- a/drivers/mtd/nand/nand_base.c
> > >> +++ b/drivers/mtd/nand/nand_base.c
> > >> @@ -4154,7 +4154,7 @@ int nand_scan_tail(struct mtd_info *mtd)
> > >>       /*
> > >>        * If no default placement scheme is given, select an appropriate one.
> > >>        */
> > >> -     if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
> > >> +     if (!mtd->ooblayout && ecc->algo != NAND_ECC_BCH) {
> > >
> > > Should be:
> > >
> > >         if (!mtd->ooblayout && ecc->algo == NAND_ECC_SOFT &&
> > >             ecc->algo != NAND_ECC_BCH) {
> > >
> > > Otherwise you're also taking the NAND_ECC_HW + NAND_ECC_BCH into
> > > account.
> > 
> > Pretty much yes, but without
> > [PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
> > we may be getting NAND_ECC_SOFT as well as NAND_ECC_SOFT_BCH. And
> > 11/12 can't be applied before 10/12. We'll need to support both values
> > for this very short moment (after 10/12 but before 11/12).
> 
> 
> Why can't you move patch 11 before patch 10. The DT parsing code has
> already been patched to set both ecc->algo to NAND_ECC_BCH and
> ecc->mode to NAND_ECC_SOFT, so, to it seems perfectly safe to reorder
> those changes to me (and change the test as suggested).
> 
> Am I missing something?
> 

Forget what I just said. How about merging those 2 patches into a
single one?

BTW, I did not complain so far, but you're trying to split every
single change into it's own patch, and I don't think it's required for
such simple change as assigning ecc->algo to NAND_ECC_BCH wherever
ecc->algo is set to NAND_ECC_SOFT_BCH (even if the patch touches
different drivers).
And the problem we're facing here is partly caused by this attempt to
split every change in its own patch.

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 10/12] mtd: nand: read ECC algorithm from the new field

[Rafał Miłecki]

On 17 April 2016 at 18:50, Boris Brezillon
<boris.brezillon@free-electrons.com> wrote:
> On Sun, 17 Apr 2016 18:27:40 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
>
>> On 16 April 2016 at 09:58, Boris Brezillon
>> <boris.brezillon@free-electrons.com> wrote:
>> > On Fri, 15 Apr 2016 21:54:10 +0200
>> > Rafał Miłecki <zajec5@gmail.com> wrote:
>> >
>> >> Now we have all drivers properly setting this new field we can start
>> >> using it and proceed with deprecating NAND_ECC_SOFT_BCH.
>> >>
>> >> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
>> >> ---
>> >>  drivers/mtd/nand/nand_base.c | 98 ++++++++++++++++++++++++--------------------
>> >>  1 file changed, 53 insertions(+), 45 deletions(-)
>> >>
>> >> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
>> >> index e1f3cf8..ffd1b32 100644
>> >> --- a/drivers/mtd/nand/nand_base.c
>> >> +++ b/drivers/mtd/nand/nand_base.c
>> >> @@ -4154,7 +4154,7 @@ int nand_scan_tail(struct mtd_info *mtd)
>> >>       /*
>> >>        * If no default placement scheme is given, select an appropriate one.
>> >>        */
>> >> -     if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
>> >> +     if (!mtd->ooblayout && ecc->algo != NAND_ECC_BCH) {
>> >
>> > Should be:
>> >
>> >         if (!mtd->ooblayout && ecc->algo == NAND_ECC_SOFT &&
>> >             ecc->algo != NAND_ECC_BCH) {
>> >
>> > Otherwise you're also taking the NAND_ECC_HW + NAND_ECC_BCH into
>> > account.
>>
>> Pretty much yes, but without
>> [PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
>> we may be getting NAND_ECC_SOFT as well as NAND_ECC_SOFT_BCH. And
>> 11/12 can't be applied before 10/12. We'll need to support both values
>> for this very short moment (after 10/12 but before 11/12).
>
>
> Why can't you move patch 11 before patch 10. The DT parsing code has
> already been patched to set both ecc->algo to NAND_ECC_BCH and
> ecc->mode to NAND_ECC_SOFT, so, to it seems perfectly safe to reorder
> those changes to me (and change the test as suggested).
>
> Am I missing something?

Without patch 10/12 we still check "mode" instead of "algo" in
nand_base.c. It means it does matter if there is NAND_ECC_SOFT or
NAND_ECC_SOFT_BCH used. We can't simply make of_get_nand_ecc_mode stop
returning NAND_ECC_SOFT_BCH without adjusting nand_base.c (as in
10/12) first.

-- 
Rafał

[PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping

[Rafał Miłecki]

There isn't any difference between handling NAND_ECC_SOFT and
NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
Please note we're keeping backward DT compatibility. We are still
treating "soft_bch" value as the one setting Hamming algorithm, it's
just handled in of_get_nand_ecc_algo now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/of/of_mtd.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 15d056e..a70a38c 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -22,7 +22,6 @@ static const char *nand_ecc_modes[] = {
 	[NAND_ECC_HW]		= "hw",
 	[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
 	[NAND_ECC_HW_OOB_FIRST]	= "hw_oob_first",
-	[NAND_ECC_SOFT_BCH]	= "soft_bch",
 };
 
 /**
@@ -45,6 +44,14 @@ int of_get_nand_ecc_mode(struct device_node *np)
 		if (!strcasecmp(pm, nand_ecc_modes[i]))
 			return i;
 
+	/*
+	 * For backward compatibility we support few obsoleted values that don't
+	 * have their mappings into nand_ecc_modes_t anymore (they were merged
+	 * with other enums).
+	 */
+	if (!strcasecmp(pm, "soft_bch"))
+		return NAND_ECC_SOFT;
+
 	return -ENODEV;
 }
 EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
-- 
1.8.4.5

Re: [PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping

[Boris Brezillon]

On Fri, 15 Apr 2016 21:54:11 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> There isn't any difference between handling NAND_ECC_SOFT and
> NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
> Please note we're keeping backward DT compatibility. We are still
> treating "soft_bch" value as the one setting Hamming algorithm, it's
> just handled in of_get_nand_ecc_algo now.
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/of/of_mtd.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c

This series is getting rid of of_mtd{.c,.h}, so I'll move those changes
directly into nand_base.c when applying.

> index 15d056e..a70a38c 100644
> --- a/drivers/of/of_mtd.c
> +++ b/drivers/of/of_mtd.c
> @@ -22,7 +22,6 @@ static const char *nand_ecc_modes[] = {
>  	[NAND_ECC_HW]		= "hw",
>  	[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
>  	[NAND_ECC_HW_OOB_FIRST]	= "hw_oob_first",
> -	[NAND_ECC_SOFT_BCH]	= "soft_bch",
>  };
>  
>  /**
> @@ -45,6 +44,14 @@ int of_get_nand_ecc_mode(struct device_node *np)
>  		if (!strcasecmp(pm, nand_ecc_modes[i]))
>  			return i;
>  
> +	/*
> +	 * For backward compatibility we support few obsoleted values that don't
> +	 * have their mappings into nand_ecc_modes_t anymore (they were merged
> +	 * with other enums).
> +	 */
> +	if (!strcasecmp(pm, "soft_bch"))
> +		return NAND_ECC_SOFT;
> +
>  	return -ENODEV;
>  }
>  EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 11/12] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping

[Boris Brezillon]

On Sat, 16 Apr 2016 10:00:43 +0200
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:

> On Fri, 15 Apr 2016 21:54:11 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
> 
> > There isn't any difference between handling NAND_ECC_SOFT and
> > NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
> > Please note we're keeping backward DT compatibility. We are still
> > treating "soft_bch" value as the one setting Hamming algorithm, it's
> > just handled in of_get_nand_ecc_algo now.
> > 
> > Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> > ---
> >  drivers/of/of_mtd.c | 9 ++++++++-
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
> 
> This series is getting rid of of_mtd{.c,.h}, so I'll move those changes
> directly into nand_base.c when applying.

Oops, here is the link:
http://lkml.iu.edu/hypermail/linux/kernel/1604.0/00298.html

> 
> > index 15d056e..a70a38c 100644
> > --- a/drivers/of/of_mtd.c
> > +++ b/drivers/of/of_mtd.c
> > @@ -22,7 +22,6 @@ static const char *nand_ecc_modes[] = {
> >  	[NAND_ECC_HW]		= "hw",
> >  	[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
> >  	[NAND_ECC_HW_OOB_FIRST]	= "hw_oob_first",
> > -	[NAND_ECC_SOFT_BCH]	= "soft_bch",
> >  };
> >  
> >  /**
> > @@ -45,6 +44,14 @@ int of_get_nand_ecc_mode(struct device_node *np)
> >  		if (!strcasecmp(pm, nand_ecc_modes[i]))
> >  			return i;
> >  
> > +	/*
> > +	 * For backward compatibility we support few obsoleted values that don't
> > +	 * have their mappings into nand_ecc_modes_t anymore (they were merged
> > +	 * with other enums).
> > +	 */
> > +	if (!strcasecmp(pm, "soft_bch"))
> > +		return NAND_ECC_SOFT;
> > +
> >  	return -ENODEV;
> >  }
> >  EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
> 
> 
> 



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 12/12] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value

[Rafał Miłecki]

This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c   | 3 +--
 drivers/mtd/nand/jz4780_nand.c | 1 -
 drivers/mtd/nand/nand_base.c   | 2 --
 drivers/mtd/nand/nandsim.c     | 2 +-
 drivers/mtd/nand/sunxi_nand.c  | 2 --
 include/linux/mtd/nand.h       | 1 -
 6 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 0f8c63f..d4f454a 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			break;
 
 		case NAND_ECC_SOFT:
-		case NAND_ECC_SOFT_BCH:
 			if (nand->ecc.algo == NAND_ECC_BCH) {
 				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 				break;
@@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		 * Don't set layout for BCH4 SW ECC. This will be
 		 * generated later in nand_bch_init() later.
 		 */
-		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
+		if (nand->ecc.mode == NAND_ECC_HW) {
 			switch (mtd->oobsize) {
 			case 16:
 			case 64:
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
index 10f249a..daf3c42 100644
--- a/drivers/mtd/nand/jz4780_nand.c
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -179,7 +179,6 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de
 		chip->ecc.correct = jz4780_nand_ecc_correct;
 		/* fall through */
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
 			(nfc->bch) ? "hardware BCH" : "software ECC",
 			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ffd1b32..186d5b5 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4248,7 +4248,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		switch (ecc->algo) {
 		case NAND_ECC_HAMMING:
 			ecc->calculate = nand_calculate_ecc;
@@ -4386,7 +4385,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 	/* Large page NAND with SOFT_ECC should support subpage reads */
 	switch (ecc->mode) {
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		if (chip->page_shift > 9)
 			chip->options |= NAND_SUBPAGE_READ;
 		break;
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index 6ff1d8d..b0074c2 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -2339,7 +2339,7 @@ static int __init ns_init_module(void)
 			retval = -EINVAL;
 			goto error;
 		}
-		chip->ecc.mode = NAND_ECC_SOFT_BCH;
+		chip->ecc.mode = NAND_ECC_SOFT;
 		chip->ecc.algo = NAND_ECC_BCH;
 		chip->ecc.size = 512;
 		chip->ecc.strength = bch;
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 1baf8983..a83a690 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1612,8 +1612,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
 		return -EINVAL;
 
 	switch (ecc->mode) {
-	case NAND_ECC_SOFT_BCH:
-		break;
 	case NAND_ECC_HW:
 		ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
 		if (ret)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index e851839..fbe8e16 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -116,7 +116,6 @@ typedef enum {
 	NAND_ECC_HW,
 	NAND_ECC_HW_SYNDROME,
 	NAND_ECC_HW_OOB_FIRST,
-	NAND_ECC_SOFT_BCH,
 } nand_ecc_modes_t;
 
 enum nand_ecc_algo {
-- 
1.8.4.5

Re: [PATCH 12/12] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value

[Boris Brezillon]

On Fri, 15 Apr 2016 21:54:12 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> This value should not be part of nand_ecc_modes_t as it specifies
> algorithm not a mode. We successfully managed to introduce new "algo"
> field which is respected now.
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/mtd/nand/fsmc_nand.c   | 3 +--
>  drivers/mtd/nand/jz4780_nand.c | 1 -
>  drivers/mtd/nand/nand_base.c   | 2 --
>  drivers/mtd/nand/nandsim.c     | 2 +-
>  drivers/mtd/nand/sunxi_nand.c  | 2 --
>  include/linux/mtd/nand.h       | 1 -
>  6 files changed, 2 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 0f8c63f..d4f454a 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>  			break;
>  
>  		case NAND_ECC_SOFT:
> -		case NAND_ECC_SOFT_BCH:
>  			if (nand->ecc.algo == NAND_ECC_BCH) {
>  				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
>  				break;
> @@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>  		 * Don't set layout for BCH4 SW ECC. This will be
>  		 * generated later in nand_bch_init() later.
>  		 */
> -		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
> +		if (nand->ecc.mode == NAND_ECC_HW) {

This test is wrong, it should be

		if (nand->ecc.mode != NAND_ECC_SOFT ||
		    nand->ecc.algo != NAND_ECC_BCH)

or
		if (!(nand->ecc.mode == NAND_ECC_SOFT &&
		      nand->ecc.algo == NAND_ECC_BCH)

>  			switch (mtd->oobsize) {
>  			case 16:
>  			case 64:
> diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
> index 10f249a..daf3c42 100644
> --- a/drivers/mtd/nand/jz4780_nand.c
> +++ b/drivers/mtd/nand/jz4780_nand.c
> @@ -179,7 +179,6 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de
>  		chip->ecc.correct = jz4780_nand_ecc_correct;
>  		/* fall through */
>  	case NAND_ECC_SOFT:
> -	case NAND_ECC_SOFT_BCH:
>  		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
>  			(nfc->bch) ? "hardware BCH" : "software ECC",
>  			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index ffd1b32..186d5b5 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -4248,7 +4248,6 @@ int nand_scan_tail(struct mtd_info *mtd)
>  		ecc->algo = NAND_ECC_HAMMING;
>  
>  	case NAND_ECC_SOFT:
> -	case NAND_ECC_SOFT_BCH:
>  		switch (ecc->algo) {
>  		case NAND_ECC_HAMMING:
>  			ecc->calculate = nand_calculate_ecc;
> @@ -4386,7 +4385,6 @@ int nand_scan_tail(struct mtd_info *mtd)
>  	/* Large page NAND with SOFT_ECC should support subpage reads */
>  	switch (ecc->mode) {
>  	case NAND_ECC_SOFT:
> -	case NAND_ECC_SOFT_BCH:
>  		if (chip->page_shift > 9)
>  			chip->options |= NAND_SUBPAGE_READ;
>  		break;
> diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
> index 6ff1d8d..b0074c2 100644
> --- a/drivers/mtd/nand/nandsim.c
> +++ b/drivers/mtd/nand/nandsim.c
> @@ -2339,7 +2339,7 @@ static int __init ns_init_module(void)
>  			retval = -EINVAL;
>  			goto error;
>  		}
> -		chip->ecc.mode = NAND_ECC_SOFT_BCH;
> +		chip->ecc.mode = NAND_ECC_SOFT;
>  		chip->ecc.algo = NAND_ECC_BCH;
>  		chip->ecc.size = 512;
>  		chip->ecc.strength = bch;
> diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
> index 1baf8983..a83a690 100644
> --- a/drivers/mtd/nand/sunxi_nand.c
> +++ b/drivers/mtd/nand/sunxi_nand.c
> @@ -1612,8 +1612,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
>  		return -EINVAL;
>  
>  	switch (ecc->mode) {
> -	case NAND_ECC_SOFT_BCH:
> -		break;
>  	case NAND_ECC_HW:
>  		ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
>  		if (ret)
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index e851839..fbe8e16 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -116,7 +116,6 @@ typedef enum {
>  	NAND_ECC_HW,
>  	NAND_ECC_HW_SYNDROME,
>  	NAND_ECC_HW_OOB_FIRST,
> -	NAND_ECC_SOFT_BCH,
>  } nand_ecc_modes_t;
>  
>  enum nand_ecc_algo {



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 12/12] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value

[Rafał Miłecki]

On 17 April 2016 at 19:05, Boris Brezillon
<boris.brezillon@free-electrons.com> wrote:
> On Fri, 15 Apr 2016 21:54:12 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
>
>> This value should not be part of nand_ecc_modes_t as it specifies
>> algorithm not a mode. We successfully managed to introduce new "algo"
>> field which is respected now.
>>
>> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
>> ---
>>  drivers/mtd/nand/fsmc_nand.c   | 3 +--
>>  drivers/mtd/nand/jz4780_nand.c | 1 -
>>  drivers/mtd/nand/nand_base.c   | 2 --
>>  drivers/mtd/nand/nandsim.c     | 2 +-
>>  drivers/mtd/nand/sunxi_nand.c  | 2 --
>>  include/linux/mtd/nand.h       | 1 -
>>  6 files changed, 2 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
>> index 0f8c63f..d4f454a 100644
>> --- a/drivers/mtd/nand/fsmc_nand.c
>> +++ b/drivers/mtd/nand/fsmc_nand.c
>> @@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>>                       break;
>>
>>               case NAND_ECC_SOFT:
>> -             case NAND_ECC_SOFT_BCH:
>>                       if (nand->ecc.algo == NAND_ECC_BCH) {
>>                               dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
>>                               break;
>> @@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>>                * Don't set layout for BCH4 SW ECC. This will be
>>                * generated later in nand_bch_init() later.
>>                */
>> -             if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
>> +             if (nand->ecc.mode == NAND_ECC_HW) {
>
> This test is wrong, it should be
>
>                 if (nand->ecc.mode != NAND_ECC_SOFT ||
>                     nand->ecc.algo != NAND_ECC_BCH)
>
> or
>                 if (!(nand->ecc.mode == NAND_ECC_SOFT &&
>                       nand->ecc.algo == NAND_ECC_BCH)

This driver supports only 2 modes (see switch above).

Re: [PATCH 12/12] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value

[Boris Brezillon]

On Sun, 17 Apr 2016 19:10:11 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> On 17 April 2016 at 19:05, Boris Brezillon
> <boris.brezillon@free-electrons.com> wrote:
> > On Fri, 15 Apr 2016 21:54:12 +0200
> > Rafał Miłecki <zajec5@gmail.com> wrote:
> >
> >> This value should not be part of nand_ecc_modes_t as it specifies
> >> algorithm not a mode. We successfully managed to introduce new "algo"
> >> field which is respected now.
> >>
> >> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> >> ---
> >>  drivers/mtd/nand/fsmc_nand.c   | 3 +--
> >>  drivers/mtd/nand/jz4780_nand.c | 1 -
> >>  drivers/mtd/nand/nand_base.c   | 2 --
> >>  drivers/mtd/nand/nandsim.c     | 2 +-
> >>  drivers/mtd/nand/sunxi_nand.c  | 2 --
> >>  include/linux/mtd/nand.h       | 1 -
> >>  6 files changed, 2 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> >> index 0f8c63f..d4f454a 100644
> >> --- a/drivers/mtd/nand/fsmc_nand.c
> >> +++ b/drivers/mtd/nand/fsmc_nand.c
> >> @@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
> >>                       break;
> >>
> >>               case NAND_ECC_SOFT:
> >> -             case NAND_ECC_SOFT_BCH:
> >>                       if (nand->ecc.algo == NAND_ECC_BCH) {
> >>                               dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
> >>                               break;
> >> @@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
> >>                * Don't set layout for BCH4 SW ECC. This will be
> >>                * generated later in nand_bch_init() later.
> >>                */
> >> -             if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
> >> +             if (nand->ecc.mode == NAND_ECC_HW) {
> >
> > This test is wrong, it should be
> >
> >                 if (nand->ecc.mode != NAND_ECC_SOFT ||
> >                     nand->ecc.algo != NAND_ECC_BCH)
> >
> > or
> >                 if (!(nand->ecc.mode == NAND_ECC_SOFT &&
> >                       nand->ecc.algo == NAND_ECC_BCH)
> 
> This driver supports only 2 modes (see switch above).

Indeed. Sorry, I didn't read the full context.

Thanks for the clarification.

Boris

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH V2 01/11] mtd: nand: bf5xx: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/bf5xx_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index b38f414..37da423 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -817,6 +817,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev)
 		chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
 	} else {
 		chip->ecc.mode	    = NAND_ECC_SOFT;
+		chip->ecc.algo	= NAND_ECC_HAMMING;
 	}
 
 	/* scan hardware nand chip and setup mtd info data struct */
-- 
1.8.4.5

[PATCH V2 02/11] mtd: nand: davinci: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 drivers/mtd/nand/davinci_nand.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index fe3fd29..b0a2801 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -738,6 +738,14 @@ static int nand_davinci_probe(struct platform_device *pdev)
 	}
 	info->chip.ecc.mode = ecc_mode;
 
+	/*
+	 * When using software ECC this driver support hamming only. Force
+	 * ecc.algo to NAND_ECC_HAMMING to avoid adding an extra ->ecc_algo
+	 * field to davinci_nand_pdata.
+	 */
+	if (ecc_mode == NAND_ECC_SOFT)
+		info->chip.ecc.algo = NAND_ECC_HAMMING;
+
 	info->clk = devm_clk_get(&pdev->dev, "aemif");
 	if (IS_ERR(info->clk)) {
 		ret = PTR_ERR(info->clk);
-- 
1.8.4.5

[PATCH V2 03/11] mtd: nand: atmel: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
V2: Set algo to Hamming based on mode being SOFT. Add a comment how to
    modify it if we ever need to.
---
 drivers/mtd/nand/atmel_nand.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index eec8ca7..efc8ea2 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1212,6 +1212,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		dev_warn(host->dev,
 			"Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1295,6 +1296,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1613,6 +1615,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * even if the nand-ecc-mode property is not defined.
 	 */
 	host->nand_chip.ecc.mode = NAND_ECC_SOFT;
+	host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
 
 	return 0;
 }
@@ -1629,6 +1632,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
 		dev_err(host->dev,
 			"Can't get I/O resource regs, use software ECC\n");
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1661,6 +1665,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -2160,6 +2165,14 @@ static int atmel_nand_probe(struct platform_device *pdev)
 		       sizeof(struct atmel_nand_data));
 		nand_chip->ecc.mode = host->board.ecc_mode;
 
+		/*
+		 * When using software ECC every supported avr32 board means
+		 * Hamming algorithm. If that ever changes we'll need to add
+		 * ecc_algo field to the struct atmel_nand_data.
+		 */
+		if (nand_chip->ecc.mode == NAND_ECC_SOFT)
+			nand_chip->ecc.algo = NAND_ECC_HAMMING;
+
 		/* 16-bit bus width */
 		if (host->board.bus_width_16)
 			nand_chip->options |= NAND_BUSWIDTH_16;
-- 
1.8.4.5

[PATCH V2 04/11] CRIS v32: nand: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 1 +
 arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
index 5aa3f51..3f646c7 100644
--- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
@@ -157,6 +157,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
 	/* 20 us command delay time */
 	this->chip_delay = 20;
 	this->ecc.mode = NAND_ECC_SOFT;
+	this->ecc.algo = NAND_ECC_HAMMING;
 
 	/* Enable the following for a flash based bad block table */
 	/* this->bbt_options = NAND_BBT_USE_FLASH; */
diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
index a7c17b0..a745405 100644
--- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
@@ -148,6 +148,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
 	/* 20 us command delay time */
 	this->chip_delay = 20;
 	this->ecc.mode = NAND_ECC_SOFT;
+	this->ecc.algo = NAND_ECC_HAMMING;
 
 	/* Enable the following for a flash based bad block table */
 	/* this->bbt_options = NAND_BBT_USE_FLASH; */
-- 
1.8.4.5

[PATCH V2 05/11] staging: mt29f_spinand: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/staging/mt29f_spinand/mt29f_spinand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/mt29f_spinand/mt29f_spinand.c b/drivers/staging/mt29f_spinand/mt29f_spinand.c
index f503699..e389009 100644
--- a/drivers/staging/mt29f_spinand/mt29f_spinand.c
+++ b/drivers/staging/mt29f_spinand/mt29f_spinand.c
@@ -900,6 +900,7 @@ static int spinand_probe(struct spi_device *spi_nand)
 	chip->ecc.write_page = spinand_write_page_hwecc;
 #else
 	chip->ecc.mode	= NAND_ECC_SOFT;
+	chip->ecc.algo	= NAND_ECC_HAMMING;
 	if (spinand_disable_ecc(spi_nand) < 0)
 		dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
 			 __func__);
-- 
1.8.4.5

[PATCH V2 06/11] mtd: nand: set ECC algorithm to Hamming on fallback

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/nand_base.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dd02c09..e1f3cf8 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4245,6 +4245,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 		pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
 			ecc->size, mtd->writesize);
 		ecc->mode = NAND_ECC_SOFT;
+		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
 		ecc->calculate = nand_calculate_ecc;
-- 
1.8.4.5

[PATCH V2 07/11] mtd: nand: hisi504: set ECC algorithm based on DT info

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
This patch may be skipped if we apply
[PATCH 00/12] mtd: get rid of of_mtd.{c,h} and of_get_nand_xx()
patchset first.
---
 drivers/mtd/nand/hisi504_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c
index 7bf844c..f917297 100644
--- a/drivers/mtd/nand/hisi504_nand.c
+++ b/drivers/mtd/nand/hisi504_nand.c
@@ -768,6 +768,7 @@ static int hisi_nfc_probe(struct platform_device *pdev)
 	chip->chip_delay	= HINFC504_CHIP_DELAY;
 
 	chip->ecc.mode = of_get_nand_ecc_mode(np);
+	chip->ecc.algo = of_get_nand_ecc_algo(np);
 
 	buswidth = of_get_nand_bus_width(np);
 	if (buswidth == 16)
-- 
1.8.4.5

[PATCH V2 08/11] mtd: nand: fsmc: validate ECC setup by checking algorithm directly

[Rafał Miłecki]

NAND core sets ECC algorithm in algo field now and it should be
preferred over the mode field. This also prepares driver for dropping
NAND_ECC_SOFT_BCH.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 1372040..0f8c63f 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -958,9 +958,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			nand->ecc.strength = 1;
 			break;
 
+		case NAND_ECC_SOFT:
 		case NAND_ECC_SOFT_BCH:
-			dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
-			break;
+			if (nand->ecc.algo == NAND_ECC_BCH) {
+				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
+				break;
+			}
 
 		default:
 			dev_err(&pdev->dev, "Unsupported ECC mode!\n");
-- 
1.8.4.5

[PATCH V2 09/11] mtd: nand: read ECC algorithm from the new field

[Rafał Miłecki]

Now we have all drivers properly setting this new field we can start
using it. For a very short period of time we should support both values:
NAND_ECC_SOFT and NAND_ECC_SOFT_BCH treating them the same. It's because
of_get_nand_ecc_mode may still be setting NAND_ECC_SOFT_BCH.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
V2: Move SOFT-related code to separated functions
    Add missing checks for SOFT before checking Hamming vs. BCH
---
 drivers/mtd/nand/nand_base.c | 116 ++++++++++++++++++++++++++-----------------
 1 file changed, 71 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index e1f3cf8..d092375 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4079,6 +4079,69 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
 }
 EXPORT_SYMBOL(nand_scan_ident);
 
+static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+	if (WARN_ON(ecc->mode != NAND_ECC_SOFT &&
+		    ecc->mode != NAND_ECC_SOFT_BCH))
+		return -EINVAL;
+
+	switch (ecc->algo) {
+	case NAND_ECC_HAMMING:
+		ecc->calculate = nand_calculate_ecc;
+		ecc->correct = nand_correct_data;
+		ecc->read_page = nand_read_page_swecc;
+		ecc->read_subpage = nand_read_subpage;
+		ecc->write_page = nand_write_page_swecc;
+		ecc->read_page_raw = nand_read_page_raw;
+		ecc->write_page_raw = nand_write_page_raw;
+		ecc->read_oob = nand_read_oob_std;
+		ecc->write_oob = nand_write_oob_std;
+		if (!ecc->size)
+			ecc->size = 256;
+		ecc->bytes = 3;
+		ecc->strength = 1;
+		return 0;
+	case NAND_ECC_BCH:
+		if (!mtd_nand_has_bch()) {
+			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
+			return -EINVAL;
+		}
+		ecc->calculate = nand_bch_calculate_ecc;
+		ecc->correct = nand_bch_correct_data;
+		ecc->read_page = nand_read_page_swecc;
+		ecc->read_subpage = nand_read_subpage;
+		ecc->write_page = nand_write_page_swecc;
+		ecc->read_page_raw = nand_read_page_raw;
+		ecc->write_page_raw = nand_write_page_raw;
+		ecc->read_oob = nand_read_oob_std;
+		ecc->write_oob = nand_write_oob_std;
+		/*
+		* Board driver should supply ecc.size and ecc.strength
+		* values to select how many bits are correctable.
+		* Otherwise, default to 4 bits for large page devices.
+		*/
+		if (!ecc->size && (mtd->oobsize >= 64)) {
+			ecc->size = 512;
+			ecc->strength = 4;
+		}
+
+		/* See nand_bch_init() for details. */
+		ecc->bytes = 0;
+		ecc->priv = nand_bch_init(mtd);
+		if (!ecc->priv) {
+			WARN(1, "BCH ECC initialization failed!\n");
+			return -EINVAL;
+		}
+		return 0;
+	default:
+		WARN(1, "Unsupported ECC algorithm!\n");
+		return -EINVAL;
+	}
+}
+
 /*
  * Check if the chip configuration meet the datasheet requirements.
 
@@ -4154,7 +4217,9 @@ int nand_scan_tail(struct mtd_info *mtd)
 	/*
 	 * If no default placement scheme is given, select an appropriate one.
 	 */
-	if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
+	if (!mtd->ooblayout &&
+	    (ecc->mode == NAND_ECC_SOFT || ecc->mode == NAND_ECC_SOFT_BCH) &&
+	    ecc->algo != NAND_ECC_BCH) {
 		switch (mtd->oobsize) {
 		case 8:
 		case 16:
@@ -4248,54 +4313,13 @@ int nand_scan_tail(struct mtd_info *mtd)
 		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
-		ecc->calculate = nand_calculate_ecc;
-		ecc->correct = nand_correct_data;
-		ecc->read_page = nand_read_page_swecc;
-		ecc->read_subpage = nand_read_subpage;
-		ecc->write_page = nand_write_page_swecc;
-		ecc->read_page_raw = nand_read_page_raw;
-		ecc->write_page_raw = nand_write_page_raw;
-		ecc->read_oob = nand_read_oob_std;
-		ecc->write_oob = nand_write_oob_std;
-		if (!ecc->size)
-			ecc->size = 256;
-		ecc->bytes = 3;
-		ecc->strength = 1;
-		break;
-
 	case NAND_ECC_SOFT_BCH:
-		if (!mtd_nand_has_bch()) {
-			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
+		ret = nand_set_ecc_soft_ops(mtd);
+		if (ret) {
 			ret = -EINVAL;
 			goto err_free;
 		}
-		ecc->calculate = nand_bch_calculate_ecc;
-		ecc->correct = nand_bch_correct_data;
-		ecc->read_page = nand_read_page_swecc;
-		ecc->read_subpage = nand_read_subpage;
-		ecc->write_page = nand_write_page_swecc;
-		ecc->read_page_raw = nand_read_page_raw;
-		ecc->write_page_raw = nand_write_page_raw;
-		ecc->read_oob = nand_read_oob_std;
-		ecc->write_oob = nand_write_oob_std;
-		/*
-		 * Board driver should supply ecc.size and ecc.strength values
-		 * to select how many bits are correctable. Otherwise, default
-		 * to 4 bits for large page devices.
-		 */
-		if (!ecc->size && (mtd->oobsize >= 64)) {
-			ecc->size = 512;
-			ecc->strength = 4;
-		}
 
-		/* See nand_bch_init() for details. */
-		ecc->bytes = 0;
-		ecc->priv = nand_bch_init(mtd);
-		if (!ecc->priv) {
-			WARN(1, "BCH ECC initialization failed!\n");
-			ret = -EINVAL;
-			goto err_free;
-		}
 		break;
 
 	case NAND_ECC_NONE:
@@ -4478,7 +4502,9 @@ void nand_release(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
-	if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
+	if ((chip->ecc.mode == NAND_ECC_SOFT ||
+	     chip->ecc.mode == NAND_ECC_SOFT_BCH) &&
+	    chip->ecc.algo == NAND_ECC_BCH)
 		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
 
 	mtd_device_unregister(mtd);
-- 
1.8.4.5

Re: [PATCH V2 09/11] mtd: nand: read ECC algorithm from the new field

[Boris Brezillon]

On Sun, 17 Apr 2016 19:11:42 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> Now we have all drivers properly setting this new field we can start
> using it. For a very short period of time we should support both values:
> NAND_ECC_SOFT and NAND_ECC_SOFT_BCH treating them the same. It's because
> of_get_nand_ecc_mode may still be setting NAND_ECC_SOFT_BCH.
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
> V2: Move SOFT-related code to separated functions
>     Add missing checks for SOFT before checking Hamming vs. BCH
> ---
>  drivers/mtd/nand/nand_base.c | 116 ++++++++++++++++++++++++++-----------------
>  1 file changed, 71 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c

[...]

>  
> @@ -4154,7 +4217,9 @@ int nand_scan_tail(struct mtd_info *mtd)
>  	/*
>  	 * If no default placement scheme is given, select an appropriate one.
>  	 */
> -	if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
> +	if (!mtd->ooblayout &&
> +	    (ecc->mode == NAND_ECC_SOFT || ecc->mode == NAND_ECC_SOFT_BCH) &&
> +	    ecc->algo != NAND_ECC_BCH) {

Sorry, I got this wrong in my previous review. It should be

	if (!mtd->ooblayout &&
	    ((ecc->mode != NAND_ECC_SOFT &&
	      ecc->mode != NAND_ECC_SOFT_BCH) ||
	     ecc->algo != NAND_ECC_BCH) {

otherwise we're only addressing the software ECC case, and IIRC, some
drivers rely on these default layouts for their HW ECC implementation.

The rest looks good to me.

Thanks,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH V2 10/11] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping

[Rafał Miłecki]

There isn't any difference between handling NAND_ECC_SOFT and
NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
Please note we're keeping backward DT compatibility. We are still
treating "soft_bch" value as the one setting Hamming algorithm, it's
just handled in of_get_nand_ecc_algo now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/of/of_mtd.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 15d056e..a70a38c 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -22,7 +22,6 @@ static const char *nand_ecc_modes[] = {
 	[NAND_ECC_HW]		= "hw",
 	[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
 	[NAND_ECC_HW_OOB_FIRST]	= "hw_oob_first",
-	[NAND_ECC_SOFT_BCH]	= "soft_bch",
 };
 
 /**
@@ -45,6 +44,14 @@ int of_get_nand_ecc_mode(struct device_node *np)
 		if (!strcasecmp(pm, nand_ecc_modes[i]))
 			return i;
 
+	/*
+	 * For backward compatibility we support few obsoleted values that don't
+	 * have their mappings into nand_ecc_modes_t anymore (they were merged
+	 * with other enums).
+	 */
+	if (!strcasecmp(pm, "soft_bch"))
+		return NAND_ECC_SOFT;
+
 	return -ENODEV;
 }
 EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
-- 
1.8.4.5

[PATCH V2 11/11] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value

[Rafał Miłecki]

This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c   |  3 +--
 drivers/mtd/nand/jz4780_nand.c |  1 -
 drivers/mtd/nand/nand_base.c   | 11 +++--------
 drivers/mtd/nand/nandsim.c     |  2 +-
 drivers/mtd/nand/sunxi_nand.c  |  2 --
 include/linux/mtd/nand.h       |  1 -
 6 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 0f8c63f..d4f454a 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			break;
 
 		case NAND_ECC_SOFT:
-		case NAND_ECC_SOFT_BCH:
 			if (nand->ecc.algo == NAND_ECC_BCH) {
 				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 				break;
@@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		 * Don't set layout for BCH4 SW ECC. This will be
 		 * generated later in nand_bch_init() later.
 		 */
-		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
+		if (nand->ecc.mode == NAND_ECC_HW) {
 			switch (mtd->oobsize) {
 			case 16:
 			case 64:
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
index 10f249a..daf3c42 100644
--- a/drivers/mtd/nand/jz4780_nand.c
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -179,7 +179,6 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de
 		chip->ecc.correct = jz4780_nand_ecc_correct;
 		/* fall through */
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
 			(nfc->bch) ? "hardware BCH" : "software ECC",
 			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d092375..bc029d0 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4084,8 +4084,7 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 
-	if (WARN_ON(ecc->mode != NAND_ECC_SOFT &&
-		    ecc->mode != NAND_ECC_SOFT_BCH))
+	if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
 		return -EINVAL;
 
 	switch (ecc->algo) {
@@ -4218,7 +4217,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 	 * If no default placement scheme is given, select an appropriate one.
 	 */
 	if (!mtd->ooblayout &&
-	    (ecc->mode == NAND_ECC_SOFT || ecc->mode == NAND_ECC_SOFT_BCH) &&
+	    ecc->mode == NAND_ECC_SOFT &&
 	    ecc->algo != NAND_ECC_BCH) {
 		switch (mtd->oobsize) {
 		case 8:
@@ -4313,13 +4312,11 @@ int nand_scan_tail(struct mtd_info *mtd)
 		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		ret = nand_set_ecc_soft_ops(mtd);
 		if (ret) {
 			ret = -EINVAL;
 			goto err_free;
 		}
-
 		break;
 
 	case NAND_ECC_NONE:
@@ -4402,7 +4399,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 	/* Large page NAND with SOFT_ECC should support subpage reads */
 	switch (ecc->mode) {
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		if (chip->page_shift > 9)
 			chip->options |= NAND_SUBPAGE_READ;
 		break;
@@ -4502,8 +4498,7 @@ void nand_release(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
-	if ((chip->ecc.mode == NAND_ECC_SOFT ||
-	     chip->ecc.mode == NAND_ECC_SOFT_BCH) &&
+	if (chip->ecc.mode == NAND_ECC_SOFT &&
 	    chip->ecc.algo == NAND_ECC_BCH)
 		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
 
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index 6ff1d8d..b0074c2 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -2339,7 +2339,7 @@ static int __init ns_init_module(void)
 			retval = -EINVAL;
 			goto error;
 		}
-		chip->ecc.mode = NAND_ECC_SOFT_BCH;
+		chip->ecc.mode = NAND_ECC_SOFT;
 		chip->ecc.algo = NAND_ECC_BCH;
 		chip->ecc.size = 512;
 		chip->ecc.strength = bch;
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 1baf8983..a83a690 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1612,8 +1612,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
 		return -EINVAL;
 
 	switch (ecc->mode) {
-	case NAND_ECC_SOFT_BCH:
-		break;
 	case NAND_ECC_HW:
 		ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
 		if (ret)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index e851839..fbe8e16 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -116,7 +116,6 @@ typedef enum {
 	NAND_ECC_HW,
 	NAND_ECC_HW_SYNDROME,
 	NAND_ECC_HW_OOB_FIRST,
-	NAND_ECC_SOFT_BCH,
 } nand_ecc_modes_t;
 
 enum nand_ecc_algo {
-- 
1.8.4.5

[PATCH V3 01/11] mtd: nand: bf5xx: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/bf5xx_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index b38f414..37da423 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -817,6 +817,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev)
 		chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
 	} else {
 		chip->ecc.mode	    = NAND_ECC_SOFT;
+		chip->ecc.algo	= NAND_ECC_HAMMING;
 	}
 
 	/* scan hardware nand chip and setup mtd info data struct */
-- 
1.8.4.5

[PATCH V3 02/11] mtd: nand: davinci: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 drivers/mtd/nand/davinci_nand.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index fe3fd29..b0a2801 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -738,6 +738,14 @@ static int nand_davinci_probe(struct platform_device *pdev)
 	}
 	info->chip.ecc.mode = ecc_mode;
 
+	/*
+	 * When using software ECC this driver support hamming only. Force
+	 * ecc.algo to NAND_ECC_HAMMING to avoid adding an extra ->ecc_algo
+	 * field to davinci_nand_pdata.
+	 */
+	if (ecc_mode == NAND_ECC_SOFT)
+		info->chip.ecc.algo = NAND_ECC_HAMMING;
+
 	info->clk = devm_clk_get(&pdev->dev, "aemif");
 	if (IS_ERR(info->clk)) {
 		ret = PTR_ERR(info->clk);
-- 
1.8.4.5

[PATCH V3 03/11] mtd: nand: atmel: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/atmel_nand.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index eec8ca7..efc8ea2 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1212,6 +1212,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		dev_warn(host->dev,
 			"Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1295,6 +1296,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1613,6 +1615,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * even if the nand-ecc-mode property is not defined.
 	 */
 	host->nand_chip.ecc.mode = NAND_ECC_SOFT;
+	host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
 
 	return 0;
 }
@@ -1629,6 +1632,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
 		dev_err(host->dev,
 			"Can't get I/O resource regs, use software ECC\n");
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -1661,6 +1665,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev,
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
 		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		nand_chip->ecc.algo = NAND_ECC_HAMMING;
 		return 0;
 	}
 
@@ -2160,6 +2165,14 @@ static int atmel_nand_probe(struct platform_device *pdev)
 		       sizeof(struct atmel_nand_data));
 		nand_chip->ecc.mode = host->board.ecc_mode;
 
+		/*
+		 * When using software ECC every supported avr32 board means
+		 * Hamming algorithm. If that ever changes we'll need to add
+		 * ecc_algo field to the struct atmel_nand_data.
+		 */
+		if (nand_chip->ecc.mode == NAND_ECC_SOFT)
+			nand_chip->ecc.algo = NAND_ECC_HAMMING;
+
 		/* 16-bit bus width */
 		if (host->board.bus_width_16)
 			nand_chip->options |= NAND_BUSWIDTH_16;
-- 
1.8.4.5

[PATCH V3 04/11] CRIS v32: nand: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 1 +
 arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
index 5aa3f51..3f646c7 100644
--- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
@@ -157,6 +157,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
 	/* 20 us command delay time */
 	this->chip_delay = 20;
 	this->ecc.mode = NAND_ECC_SOFT;
+	this->ecc.algo = NAND_ECC_HAMMING;
 
 	/* Enable the following for a flash based bad block table */
 	/* this->bbt_options = NAND_BBT_USE_FLASH; */
diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
index a7c17b0..a745405 100644
--- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
@@ -148,6 +148,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
 	/* 20 us command delay time */
 	this->chip_delay = 20;
 	this->ecc.mode = NAND_ECC_SOFT;
+	this->ecc.algo = NAND_ECC_HAMMING;
 
 	/* Enable the following for a flash based bad block table */
 	/* this->bbt_options = NAND_BBT_USE_FLASH; */
-- 
1.8.4.5

Re: [PATCH V3 04/11] CRIS v32: nand: set ECC algorithm explicitly

[Boris Brezillon]

On Sun, 17 Apr 2016 22:53:00 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

Mikael, Jesper, could you review/ack this patch? I'd like to take it
into the nand tree to avoid any dependency problems.

Thanks,

Boris

> ---
>  arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 1 +
>  arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> index 5aa3f51..3f646c7 100644
> --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> +++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> @@ -157,6 +157,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
>  	/* 20 us command delay time */
>  	this->chip_delay = 20;
>  	this->ecc.mode = NAND_ECC_SOFT;
> +	this->ecc.algo = NAND_ECC_HAMMING;
>  
>  	/* Enable the following for a flash based bad block table */
>  	/* this->bbt_options = NAND_BBT_USE_FLASH; */
> diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> index a7c17b0..a745405 100644
> --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> +++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> @@ -148,6 +148,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
>  	/* 20 us command delay time */
>  	this->chip_delay = 20;
>  	this->ecc.mode = NAND_ECC_SOFT;
> +	this->ecc.algo = NAND_ECC_HAMMING;
>  
>  	/* Enable the following for a flash based bad block table */
>  	/* this->bbt_options = NAND_BBT_USE_FLASH; */



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH V3 04/11] CRIS v32: nand: set ECC algorithm explicitly

[Mikael Starvik]

Acked-by: Mikael Starvik <starvik@axis.com>

> 17 apr. 2016 kl. 22:53 skrev Rafał Miłecki <zajec5@gmail.com>:
> 
> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
> arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 1 +
> arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 1 +
> 2 files changed, 2 insertions(+)
> 
> diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> index 5aa3f51..3f646c7 100644
> --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> +++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> @@ -157,6 +157,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
>   /* 20 us command delay time */
>   this->chip_delay = 20;
>   this->ecc.mode = NAND_ECC_SOFT;
> +    this->ecc.algo = NAND_ECC_HAMMING;
> 
>   /* Enable the following for a flash based bad block table */
>   /* this->bbt_options = NAND_BBT_USE_FLASH; */
> diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> index a7c17b0..a745405 100644
> --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> +++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> @@ -148,6 +148,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
>   /* 20 us command delay time */
>   this->chip_delay = 20;
>   this->ecc.mode = NAND_ECC_SOFT;
> +    this->ecc.algo = NAND_ECC_HAMMING;
> 
>   /* Enable the following for a flash based bad block table */
>   /* this->bbt_options = NAND_BBT_USE_FLASH; */
> -- 
> 1.8.4.5
> 

Re: [PATCH V3 04/11] CRIS v32: nand: set ECC algorithm explicitly

[Jesper Nilsson]

On Sun, Apr 17, 2016 at 10:53:00PM +0200, Rafał Miłecki wrote:
> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>


/^JN - Jesper Nilsson
-- 
               Jesper Nilsson -- jesper.nilsson@axis.com

[PATCH V3 05/11] staging: mt29f_spinand: set ECC algorithm explicitly

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/staging/mt29f_spinand/mt29f_spinand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/mt29f_spinand/mt29f_spinand.c b/drivers/staging/mt29f_spinand/mt29f_spinand.c
index f503699..e389009 100644
--- a/drivers/staging/mt29f_spinand/mt29f_spinand.c
+++ b/drivers/staging/mt29f_spinand/mt29f_spinand.c
@@ -900,6 +900,7 @@ static int spinand_probe(struct spi_device *spi_nand)
 	chip->ecc.write_page = spinand_write_page_hwecc;
 #else
 	chip->ecc.mode	= NAND_ECC_SOFT;
+	chip->ecc.algo	= NAND_ECC_HAMMING;
 	if (spinand_disable_ecc(spi_nand) < 0)
 		dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
 			 __func__);
-- 
1.8.4.5

Re: [PATCH V3 05/11] staging: mt29f_spinand: set ECC algorithm explicitly

[Boris Brezillon]

Hi Greg,

On Sun, 17 Apr 2016 22:53:01 +0200
Rafał Miłecki <zajec5@gmail.com> wrote:

> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).

Do you mind if I take this patch through the NAND tree in order to avoid
dependency problems?

> 
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/staging/mt29f_spinand/mt29f_spinand.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/staging/mt29f_spinand/mt29f_spinand.c b/drivers/staging/mt29f_spinand/mt29f_spinand.c
> index f503699..e389009 100644
> --- a/drivers/staging/mt29f_spinand/mt29f_spinand.c
> +++ b/drivers/staging/mt29f_spinand/mt29f_spinand.c
> @@ -900,6 +900,7 @@ static int spinand_probe(struct spi_device *spi_nand)
>  	chip->ecc.write_page = spinand_write_page_hwecc;
>  #else
>  	chip->ecc.mode	= NAND_ECC_SOFT;
> +	chip->ecc.algo	= NAND_ECC_HAMMING;
>  	if (spinand_disable_ecc(spi_nand) < 0)
>  		dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
>  			 __func__);



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH V3 05/11] staging: mt29f_spinand: set ECC algorithm explicitly

[Greg Kroah-Hartman]

On Thu, Apr 21, 2016 at 10:20:56PM +0200, Boris Brezillon wrote:
> Hi Greg,
> 
> On Sun, 17 Apr 2016 22:53:01 +0200
> Rafał Miłecki <zajec5@gmail.com> wrote:
> 
> > This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> > enum nand_ecc_algo).
> 
> Do you mind if I take this patch through the NAND tree in order to avoid
> dependency problems?

Not at all:
	Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH V3 06/11] mtd: nand: set ECC algorithm to Hamming on fallback

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/nand_base.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dd02c09..e1f3cf8 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4245,6 +4245,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 		pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
 			ecc->size, mtd->writesize);
 		ecc->mode = NAND_ECC_SOFT;
+		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
 		ecc->calculate = nand_calculate_ecc;
-- 
1.8.4.5

[PATCH V3 07/11] mtd: nand: hisi504: set ECC algorithm based on DT info

[Rafał Miłecki]

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
This patch may be skipped if we apply
[PATCH 00/12] mtd: get rid of of_mtd.{c,h} and of_get_nand_xx()
patchset first.
---
 drivers/mtd/nand/hisi504_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c
index 7bf844c..f917297 100644
--- a/drivers/mtd/nand/hisi504_nand.c
+++ b/drivers/mtd/nand/hisi504_nand.c
@@ -768,6 +768,7 @@ static int hisi_nfc_probe(struct platform_device *pdev)
 	chip->chip_delay	= HINFC504_CHIP_DELAY;
 
 	chip->ecc.mode = of_get_nand_ecc_mode(np);
+	chip->ecc.algo = of_get_nand_ecc_algo(np);
 
 	buswidth = of_get_nand_bus_width(np);
 	if (buswidth == 16)
-- 
1.8.4.5

[PATCH V3 08/11] mtd: nand: fsmc: validate ECC setup by checking algorithm directly

[Rafał Miłecki]

NAND core sets ECC algorithm in algo field now and it should be
preferred over the mode field. This also prepares driver for dropping
NAND_ECC_SOFT_BCH.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 1372040..0f8c63f 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -958,9 +958,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			nand->ecc.strength = 1;
 			break;
 
+		case NAND_ECC_SOFT:
 		case NAND_ECC_SOFT_BCH:
-			dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
-			break;
+			if (nand->ecc.algo == NAND_ECC_BCH) {
+				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
+				break;
+			}
 
 		default:
 			dev_err(&pdev->dev, "Unsupported ECC mode!\n");
-- 
1.8.4.5

[PATCH V3 09/11] mtd: nand: read ECC algorithm from the new field

[Rafał Miłecki]

Now we have all drivers properly setting this new field we can start
using it. For a very short period of time we should support both values:
NAND_ECC_SOFT and NAND_ECC_SOFT_BCH treating them the same. It's because
of_get_nand_ecc_mode may still be setting NAND_ECC_SOFT_BCH.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
V2: Move SOFT-related code to separated functions
    Add missing checks for SOFT before checking Hamming vs. BCH
V3: Fix condition for "no default placement scheme" case
---
 drivers/mtd/nand/nand_base.c | 116 ++++++++++++++++++++++++++-----------------
 1 file changed, 71 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index e1f3cf8..e51d927 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4079,6 +4079,69 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
 }
 EXPORT_SYMBOL(nand_scan_ident);
 
+static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+	if (WARN_ON(ecc->mode != NAND_ECC_SOFT &&
+		    ecc->mode != NAND_ECC_SOFT_BCH))
+		return -EINVAL;
+
+	switch (ecc->algo) {
+	case NAND_ECC_HAMMING:
+		ecc->calculate = nand_calculate_ecc;
+		ecc->correct = nand_correct_data;
+		ecc->read_page = nand_read_page_swecc;
+		ecc->read_subpage = nand_read_subpage;
+		ecc->write_page = nand_write_page_swecc;
+		ecc->read_page_raw = nand_read_page_raw;
+		ecc->write_page_raw = nand_write_page_raw;
+		ecc->read_oob = nand_read_oob_std;
+		ecc->write_oob = nand_write_oob_std;
+		if (!ecc->size)
+			ecc->size = 256;
+		ecc->bytes = 3;
+		ecc->strength = 1;
+		return 0;
+	case NAND_ECC_BCH:
+		if (!mtd_nand_has_bch()) {
+			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
+			return -EINVAL;
+		}
+		ecc->calculate = nand_bch_calculate_ecc;
+		ecc->correct = nand_bch_correct_data;
+		ecc->read_page = nand_read_page_swecc;
+		ecc->read_subpage = nand_read_subpage;
+		ecc->write_page = nand_write_page_swecc;
+		ecc->read_page_raw = nand_read_page_raw;
+		ecc->write_page_raw = nand_write_page_raw;
+		ecc->read_oob = nand_read_oob_std;
+		ecc->write_oob = nand_write_oob_std;
+		/*
+		* Board driver should supply ecc.size and ecc.strength
+		* values to select how many bits are correctable.
+		* Otherwise, default to 4 bits for large page devices.
+		*/
+		if (!ecc->size && (mtd->oobsize >= 64)) {
+			ecc->size = 512;
+			ecc->strength = 4;
+		}
+
+		/* See nand_bch_init() for details. */
+		ecc->bytes = 0;
+		ecc->priv = nand_bch_init(mtd);
+		if (!ecc->priv) {
+			WARN(1, "BCH ECC initialization failed!\n");
+			return -EINVAL;
+		}
+		return 0;
+	default:
+		WARN(1, "Unsupported ECC algorithm!\n");
+		return -EINVAL;
+	}
+}
+
 /*
  * Check if the chip configuration meet the datasheet requirements.
 
@@ -4154,7 +4217,9 @@ int nand_scan_tail(struct mtd_info *mtd)
 	/*
 	 * If no default placement scheme is given, select an appropriate one.
 	 */
-	if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
+	if (!mtd->ooblayout &&
+	    !((ecc->mode == NAND_ECC_SOFT || ecc->mode == NAND_ECC_SOFT_BCH) &&
+	       ecc->algo == NAND_ECC_BCH)) {
 		switch (mtd->oobsize) {
 		case 8:
 		case 16:
@@ -4248,54 +4313,13 @@ int nand_scan_tail(struct mtd_info *mtd)
 		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
-		ecc->calculate = nand_calculate_ecc;
-		ecc->correct = nand_correct_data;
-		ecc->read_page = nand_read_page_swecc;
-		ecc->read_subpage = nand_read_subpage;
-		ecc->write_page = nand_write_page_swecc;
-		ecc->read_page_raw = nand_read_page_raw;
-		ecc->write_page_raw = nand_write_page_raw;
-		ecc->read_oob = nand_read_oob_std;
-		ecc->write_oob = nand_write_oob_std;
-		if (!ecc->size)
-			ecc->size = 256;
-		ecc->bytes = 3;
-		ecc->strength = 1;
-		break;
-
 	case NAND_ECC_SOFT_BCH:
-		if (!mtd_nand_has_bch()) {
-			WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
+		ret = nand_set_ecc_soft_ops(mtd);
+		if (ret) {
 			ret = -EINVAL;
 			goto err_free;
 		}
-		ecc->calculate = nand_bch_calculate_ecc;
-		ecc->correct = nand_bch_correct_data;
-		ecc->read_page = nand_read_page_swecc;
-		ecc->read_subpage = nand_read_subpage;
-		ecc->write_page = nand_write_page_swecc;
-		ecc->read_page_raw = nand_read_page_raw;
-		ecc->write_page_raw = nand_write_page_raw;
-		ecc->read_oob = nand_read_oob_std;
-		ecc->write_oob = nand_write_oob_std;
-		/*
-		 * Board driver should supply ecc.size and ecc.strength values
-		 * to select how many bits are correctable. Otherwise, default
-		 * to 4 bits for large page devices.
-		 */
-		if (!ecc->size && (mtd->oobsize >= 64)) {
-			ecc->size = 512;
-			ecc->strength = 4;
-		}
 
-		/* See nand_bch_init() for details. */
-		ecc->bytes = 0;
-		ecc->priv = nand_bch_init(mtd);
-		if (!ecc->priv) {
-			WARN(1, "BCH ECC initialization failed!\n");
-			ret = -EINVAL;
-			goto err_free;
-		}
 		break;
 
 	case NAND_ECC_NONE:
@@ -4478,7 +4502,9 @@ void nand_release(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
-	if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
+	if ((chip->ecc.mode == NAND_ECC_SOFT ||
+	     chip->ecc.mode == NAND_ECC_SOFT_BCH) &&
+	    chip->ecc.algo == NAND_ECC_BCH)
 		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
 
 	mtd_device_unregister(mtd);
-- 
1.8.4.5

[PATCH V3 10/11] of: mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping

[Rafał Miłecki]

There isn't any difference between handling NAND_ECC_SOFT and
NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
Please note we're keeping backward DT compatibility. We are still
treating "soft_bch" value as the one setting Hamming algorithm, it's
just handled in of_get_nand_ecc_algo now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/of/of_mtd.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 15d056e..a70a38c 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -22,7 +22,6 @@ static const char *nand_ecc_modes[] = {
 	[NAND_ECC_HW]		= "hw",
 	[NAND_ECC_HW_SYNDROME]	= "hw_syndrome",
 	[NAND_ECC_HW_OOB_FIRST]	= "hw_oob_first",
-	[NAND_ECC_SOFT_BCH]	= "soft_bch",
 };
 
 /**
@@ -45,6 +44,14 @@ int of_get_nand_ecc_mode(struct device_node *np)
 		if (!strcasecmp(pm, nand_ecc_modes[i]))
 			return i;
 
+	/*
+	 * For backward compatibility we support few obsoleted values that don't
+	 * have their mappings into nand_ecc_modes_t anymore (they were merged
+	 * with other enums).
+	 */
+	if (!strcasecmp(pm, "soft_bch"))
+		return NAND_ECC_SOFT;
+
 	return -ENODEV;
 }
 EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
-- 
1.8.4.5

[PATCH V3 11/11] mtd: mtd: drop NAND_ECC_SOFT_BCH enum value

[Rafał Miłecki]

This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c   |  3 +--
 drivers/mtd/nand/jz4780_nand.c |  1 -
 drivers/mtd/nand/nand_base.c   | 12 +++---------
 drivers/mtd/nand/nandsim.c     |  2 +-
 drivers/mtd/nand/sunxi_nand.c  |  2 --
 include/linux/mtd/nand.h       |  1 -
 6 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 0f8c63f..d4f454a 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -959,7 +959,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			break;
 
 		case NAND_ECC_SOFT:
-		case NAND_ECC_SOFT_BCH:
 			if (nand->ecc.algo == NAND_ECC_BCH) {
 				dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 				break;
@@ -974,7 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		 * Don't set layout for BCH4 SW ECC. This will be
 		 * generated later in nand_bch_init() later.
 		 */
-		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
+		if (nand->ecc.mode == NAND_ECC_HW) {
 			switch (mtd->oobsize) {
 			case 16:
 			case 64:
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
index 10f249a..daf3c42 100644
--- a/drivers/mtd/nand/jz4780_nand.c
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -179,7 +179,6 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de
 		chip->ecc.correct = jz4780_nand_ecc_correct;
 		/* fall through */
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
 			(nfc->bch) ? "hardware BCH" : "software ECC",
 			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index e51d927..e40832d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4084,8 +4084,7 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 
-	if (WARN_ON(ecc->mode != NAND_ECC_SOFT &&
-		    ecc->mode != NAND_ECC_SOFT_BCH))
+	if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
 		return -EINVAL;
 
 	switch (ecc->algo) {
@@ -4218,8 +4217,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 	 * If no default placement scheme is given, select an appropriate one.
 	 */
 	if (!mtd->ooblayout &&
-	    !((ecc->mode == NAND_ECC_SOFT || ecc->mode == NAND_ECC_SOFT_BCH) &&
-	       ecc->algo == NAND_ECC_BCH)) {
+	    !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
 		switch (mtd->oobsize) {
 		case 8:
 		case 16:
@@ -4313,13 +4311,11 @@ int nand_scan_tail(struct mtd_info *mtd)
 		ecc->algo = NAND_ECC_HAMMING;
 
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		ret = nand_set_ecc_soft_ops(mtd);
 		if (ret) {
 			ret = -EINVAL;
 			goto err_free;
 		}
-
 		break;
 
 	case NAND_ECC_NONE:
@@ -4402,7 +4398,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 	/* Large page NAND with SOFT_ECC should support subpage reads */
 	switch (ecc->mode) {
 	case NAND_ECC_SOFT:
-	case NAND_ECC_SOFT_BCH:
 		if (chip->page_shift > 9)
 			chip->options |= NAND_SUBPAGE_READ;
 		break;
@@ -4502,8 +4497,7 @@ void nand_release(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
-	if ((chip->ecc.mode == NAND_ECC_SOFT ||
-	     chip->ecc.mode == NAND_ECC_SOFT_BCH) &&
+	if (chip->ecc.mode == NAND_ECC_SOFT &&
 	    chip->ecc.algo == NAND_ECC_BCH)
 		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
 
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index 6ff1d8d..b0074c2 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -2339,7 +2339,7 @@ static int __init ns_init_module(void)
 			retval = -EINVAL;
 			goto error;
 		}
-		chip->ecc.mode = NAND_ECC_SOFT_BCH;
+		chip->ecc.mode = NAND_ECC_SOFT;
 		chip->ecc.algo = NAND_ECC_BCH;
 		chip->ecc.size = 512;
 		chip->ecc.strength = bch;
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 1baf8983..a83a690 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1612,8 +1612,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
 		return -EINVAL;
 
 	switch (ecc->mode) {
-	case NAND_ECC_SOFT_BCH:
-		break;
 	case NAND_ECC_HW:
 		ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
 		if (ret)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index e851839..fbe8e16 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -116,7 +116,6 @@ typedef enum {
 	NAND_ECC_HW,
 	NAND_ECC_HW_SYNDROME,
 	NAND_ECC_HW_OOB_FIRST,
-	NAND_ECC_SOFT_BCH,
 } nand_ecc_modes_t;
 
 enum nand_ecc_algo {
-- 
1.8.4.5