From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754296AbcDVOc3 (ORCPT ); Fri, 22 Apr 2016 10:32:29 -0400 Received: from merlin.infradead.org ([205.233.59.134]:41240 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754260AbcDVOc0 (ORCPT ); Fri, 22 Apr 2016 10:32:26 -0400 Date: Fri, 22 Apr 2016 16:32:22 +0200 From: Peter Zijlstra To: Will Deacon Cc: linux-kernel@vger.kernel.org, "Paul E. McKenney" Subject: Re: [PATCH] documentation: ACQUIRE applies to loads, RELEASE applies to stores Message-ID: <20160422143222.GU3430@twins.programming.kicks-ass.net> References: <1461321709-16619-1-git-send-email-will.deacon@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1461321709-16619-1-git-send-email-will.deacon@arm.com> User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 22, 2016 at 11:41:49AM +0100, Will Deacon wrote: > For compound atomics performing both a load and a store operation, make > it clear that _acquire and _release variants refer only to the load and > store portions of compound atomic. For example, xchg_acquire is an xchg > operation where the load takes on ACQUIRE semantics. > > Cc: Paul E. McKenney Thanks! Acked-by: Peter Zijlstra (Intel) > Signed-off-by: Will Deacon > --- > Documentation/memory-barriers.txt | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > index 3729cbe60e41..05f8011011be 100644 > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -464,6 +464,11 @@ And a couple of implicit varieties: > This means that ACQUIRE acts as a minimal "acquire" operation and > RELEASE acts as a minimal "release" operation. > > +A subset of the atomic operations described in atomic_ops.txt have ACQUIRE > +and RELEASE variants in addition to fully-ordered and relaxed (no barrier > +semantics) definitions. For compound atomics performing both a load and a > +store, ACQUIRE semantics apply only to the load and RELEASE semantics apply > +only to the store portion of the operation. > > Memory barriers are only required where there's a possibility of interaction > between two CPUs or between a CPU and a device. If it can be guaranteed that > -- > 2.1.4 >