From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753835AbcEBLOA (ORCPT ); Mon, 2 May 2016 07:14:00 -0400 Received: from down.free-electrons.com ([37.187.137.238]:50455 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753781AbcEBLNv (ORCPT ); Mon, 2 May 2016 07:13:51 -0400 Date: Mon, 2 May 2016 13:13:37 +0200 From: Maxime Ripard To: Vishnu Patekar Cc: emilio@elopez.com.ar, wens@csie.org, sboyd@codeaurora.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2] clk: sunxi: predivider handling for factors clock Message-ID: <20160502111337.GR17159@lukather> References: <1461084466-20889-1-git-send-email-vishnupatekar0510@gmail.com> <1461084466-20889-2-git-send-email-vishnupatekar0510@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="D+M1YvVlDncl3vD5" Content-Disposition: inline In-Reply-To: <1461084466-20889-2-git-send-email-vishnupatekar0510@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --D+M1YvVlDncl3vD5 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Apr 20, 2016 at 12:47:46AM +0800, Vishnu Patekar wrote: > For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent. > To handle this, this patch adds predivider table with parent index, > prediv shift and width, parents with predivider will have nonzero width. >=20 > Rate adjustment is moved from clock specific recalc function to generic > factors recalc. Also, adds prediv table for a31. >=20 > Signed-off-by: Vishnu Patekar > --- > drivers/clk/sunxi/clk-factors.c | 31 +++++++++++++++---------------- > drivers/clk/sunxi/clk-factors.h | 10 +++++++++- > drivers/clk/sunxi/clk-sunxi.c | 31 +++++++++---------------------- > 3 files changed, 33 insertions(+), 39 deletions(-) >=20 > diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-fact= ors.c > index ddefe96..8f3b637 100644 > --- a/drivers/clk/sunxi/clk-factors.c > +++ b/drivers/clk/sunxi/clk-factors.c > @@ -45,10 +45,12 @@ static unsigned long clk_factors_recalc_rate(struct c= lk_hw *hw, > unsigned long parent_rate) > { > u8 n =3D 1, k =3D 0, p =3D 0, m =3D 0; > + u8 par_index =3D 0; > u32 reg; > unsigned long rate; > struct clk_factors *factors =3D to_clk_factors(hw); > const struct clk_factors_config *config =3D factors->config; > + const struct clk_factors_prediv *prediv =3D factors->prediv_config; > =20 > /* Fetch the register value */ > reg =3D readl(factors->reg); > @@ -63,24 +65,16 @@ static unsigned long clk_factors_recalc_rate(struct c= lk_hw *hw, > if (config->pwidth !=3D SUNXI_FACTORS_NOT_APPLICABLE) > p =3D FACTOR_GET(config->pshift, config->pwidth, reg); > =20 > - if (factors->recalc) { > - struct factors_request factors_req =3D { > - .parent_rate =3D parent_rate, > - .n =3D n, > - .k =3D k, > - .m =3D m, > - .p =3D p, > - }; > - > + if (prediv) { > /* get mux details from mux clk structure */ > if (factors->mux) > - factors_req.parent_index =3D > - (reg >> factors->mux->shift) & > - factors->mux->mask; > - > - factors->recalc(&factors_req); > + par_index =3D (reg >> factors->mux->shift) & > + factors->mux->mask; > =20 > - return factors_req.rate; > + if (prediv[par_index].width !=3D SUNXI_FACTORS_NOT_APPLICABLE) { > + m =3D FACTOR_GET(prediv[par_index].shift, > + prediv[par_index].width, reg); > + } > } > =20 > /* Calculate the rate */ > @@ -102,8 +96,12 @@ static int clk_factors_determine_rate(struct clk_hw *= hw, > for (i =3D 0; i < num_parents; i++) { > struct factors_request factors_req =3D { > .rate =3D req->rate, > - .parent_index =3D i, > }; > + > + if (factors->prediv_config) > + factors_req.prediv_width =3D > + factors->prediv_config[i].width; > + > parent =3D clk_hw_get_parent_by_index(hw, i); > if (!parent) > continue; > @@ -211,6 +209,7 @@ struct clk *sunxi_factors_register(struct device_node= *node, > /* set up factors properties */ > factors->reg =3D reg; > factors->config =3D data->table; > + factors->prediv_config =3D data->prediv_table; > factors->get_factors =3D data->getter; > factors->recalc =3D data->recalc; > factors->lock =3D lock; > diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-fact= ors.h > index 1e63c5b..b1b7745 100644 > --- a/drivers/clk/sunxi/clk-factors.h > +++ b/drivers/clk/sunxi/clk-factors.h > @@ -18,10 +18,16 @@ struct clk_factors_config { > u8 n_start; > }; > =20 > +struct clk_factors_prediv { > + u8 parent_index; > + u8 shift; > + u8 width; > +}; > + > struct factors_request { > unsigned long rate; > unsigned long parent_rate; > - u8 parent_index; > + u8 prediv_width; > u8 n; > u8 k; > u8 m; > @@ -33,6 +39,7 @@ struct factors_data { > int mux; > int muxmask; > const struct clk_factors_config *table; > + const struct clk_factors_prediv *prediv_table; > void (*getter)(struct factors_request *req); > void (*recalc)(struct factors_request *req); > const char *name; > @@ -42,6 +49,7 @@ struct clk_factors { > struct clk_hw hw; > void __iomem *reg; > const struct clk_factors_config *config; > + const struct clk_factors_prediv *prediv_config; > void (*get_factors)(struct factors_request *req); > void (*recalc)(struct factors_request *req); > spinlock_t *lock; > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c > index 91de0a0..5a5f26b 100644 > --- a/drivers/clk/sunxi/clk-sunxi.c > +++ b/drivers/clk/sunxi/clk-sunxi.c > @@ -282,8 +282,6 @@ static void sun5i_a13_get_ahb_factors(struct factors_= request *req) > req->p =3D div; > } > =20 > -#define SUN6I_AHB1_PARENT_PLL6 3 > - > /** > * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB > * AHB rate is calculated as follows > @@ -307,7 +305,7 @@ static void sun6i_get_ahb1_factors(struct factors_req= uest *req) > div =3D DIV_ROUND_UP(req->parent_rate, req->rate); > =20 > /* calculate pre-divider if parent is pll6 */ > - if (req->parent_index =3D=3D SUN6I_AHB1_PARENT_PLL6) { > + if (req->prediv_width) { > if (div < 4) > calcp =3D 0; > else if (div / 2 < 4) You should also remove that code from that function. Now that the core can tell the pre-divider configuration, it can adjust the parent rate so that you don't have to care anymore. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --D+M1YvVlDncl3vD5 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXJzZhAAoJEBx+YmzsjxAgiIYP/1WST/aVx+41nSKUAGthsWSN HNeNV8ob1lxHDKLc7fvOlgoYnUKtxI9GhEweJ1DPYTUhBIh5Z6wB8GWEt257tznH 1HjM4E+hgaynQdUSzKdHQXW0INsvFE0IVhuDEH8Pfhhur1B6P4cs7/YGdLEGMhnM KhbgGv7/VZZOvyMlfS7bX3nGgQ9n6KK7t4Pv7pN2zWcwvbM2lZcWODOCVzRSNDFO sio/O5oWNf6XoZVzizCTaEs+Pdw3vIQ7J6V2GGXQPQ1c8BHnkBhh6YIwGk/7fchY +PZQTyyuiyO5KkBkIX2mYSeuUXu/XQRTHlErrIZeEqZ3IQzyNH9cG5jTxvdFn2kI 6DoHPlQTzztK2Te2PnIMAG0fDn1IiVRIPVGPfgcoqLUbDAIwr97+xpJnG93dAEuk GlXbqTjUpA5cY7Z/fOrWlQxvUfdzsnFluiPr++VtOBIRq2p8IVtC80tk10bBn2uk 8keAE/DQUSoYzJWUA+vcBw4HRR7j0bGbrwSje+x8Pd1yBt00EGsERp6YHlc2Hs5a +qg94oiKe+KjWUWzwG9rJzo/O8CVT02dSXo9mNHoTzX0p95ld2rsmcalrhQKCFs4 0XYt+uqZj3hwAq/ZDEGgyEJqj8fnqwVWz9e7h3ntlIxltDZuvn1qgAr04mtvwHtd F4ARn+WeccPYOsil7A+2 =f7ID -----END PGP SIGNATURE----- --D+M1YvVlDncl3vD5--