From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755519AbcECIdK (ORCPT ); Tue, 3 May 2016 04:33:10 -0400 Received: from mail.kernel.org ([198.145.29.136]:59353 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750819AbcECIdI (ORCPT ); Tue, 3 May 2016 04:33:08 -0400 Date: Tue, 3 May 2016 16:32:53 +0800 From: Shawn Guo To: Stefan Agner , Anson Huang , Adrian Alonso , Frank Li Cc: kernel@pengutronix.de, mturquette@baylibre.com, sboyd@codeaurora.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: imx: fix ahb clock mux 1 Message-ID: <20160503083253.GC5874@tiger> References: <1461877623-26838-1-git-send-email-stefan@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1461877623-26838-1-git-send-email-stefan@agner.ch> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote: > The clock parent of the AHB root clock when using mux option 1 > is the SYS PLL 270MHz clock. This is specified in Table 5-11 > Clock Root Table of the i.MX 7Dual Applications Processor > Reference Manual. > > While it could be a documentation error, the 270MHz parent is > also mentioned in the boot ROM configuration in Table 6-28: The > clock is by default at 135MHz due to a POST_PODF value of 1 > (=> divider of 2). > > Signed-off-by: Stefan Agner Anson, Frank, Can you guys confirm this change is correct? Shawn > --- > Hi Shawn, > > I did not found a clock which was based on this clock which I > could measure externally... But the change is backed by the > documentation. > > -- > Stefan > > drivers/clk/imx/clk-imx7d.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c > index 7912be8..5229968 100644 > --- a/drivers/clk/imx/clk-imx7d.c > +++ b/drivers/clk/imx/clk-imx7d.c > @@ -56,7 +56,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", > "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", > "pll_audio_main_clk", }; > > -static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk", > +static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", > "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", > "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk", > "pll_video_main_clk", }; > -- > 2.8.0 > >