From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752844AbcEIKrc (ORCPT ); Mon, 9 May 2016 06:47:32 -0400 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:35901 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751420AbcEIKr2 (ORCPT ); Mon, 9 May 2016 06:47:28 -0400 Authentication-Results: ppops.net; spf=none smtp.mailfrom=ckeepax@opensource.wolfsonmicro.com Date: Mon, 9 May 2016 11:47:28 +0100 From: Charles Keepax To: Stephen Boyd CC: , , , , , , , Subject: Re: [PATCH v3 2/4] clk: arizona: Add clock driver for the Arizona devices Message-ID: <20160509104728.GG1646@localhost.localdomain> References: <1452252582-20834-1-git-send-email-ckeepax@opensource.wolfsonmicro.com> <1452252582-20834-2-git-send-email-ckeepax@opensource.wolfsonmicro.com> <20160507005501.GN3492@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20160507005501.GN3492@codeaurora.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 impostorscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1603290000 definitions=main-1605090160 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 06, 2016 at 05:55:01PM -0700, Stephen Boyd wrote: > I've applied this to clk-next but still have a question, see > below. > > On 01/08, Charles Keepax wrote: > > diff --git a/drivers/clk/clk-arizona.c b/drivers/clk/clk-arizona.c > > new file mode 100644 > > index 0000000..eaf2877 > > --- /dev/null > > +++ b/drivers/clk/clk-arizona.c > > + > > +static int arizona_clk_of_get_pdata(struct arizona *arizona) > > +{ > > + const char * const pins[] = { "mclk1", "mclk2" }; > > + struct clk *mclk; > > + int i; > > + > > + if (!of_property_read_bool(arizona->dev->of_node, "clocks")) > > + return 0; > > + > > + for (i = 0; i < ARRAY_SIZE(pins); ++i) { > > + mclk = of_clk_get_by_name(arizona->dev->of_node, pins[i]); > > + if (IS_ERR(mclk)) > > + return PTR_ERR(mclk); > > + > > + if (clk_get_rate(mclk) == CLK32K_RATE) { > > + arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK1 + i; > > + arizona->pdata.clk32k_parent = __clk_get_name(mclk); > > + } > > + > > + clk_put(mclk); > > Could this be done through assigned parents instead of this rate > checking stuff? Presumably DT could tell us how the clk tree > should be configured. > Apologies, I have been working on a v4 that includes these improvements. It does indeed look much nicer using assigned parents etc. I think it might be best to drop these for now until those are ready to send. The only problem I really have left to sort out before I can send it are some locking issues. It is quite tricky to get interaction between the clocking and SPI frameworks to play nicely. The SPI framework will sometimes punt the actually processing for the transfer to a worker thread which will often perform operations on clocks required for the SPI. Because this is a seperate thread it isn't handled by the re-enterant locking in the clock framework. I had been working around this using async transfers for the SPI, but even then I have since found you can get lockdep warnings because of the potential mutex inversion (SPI mutex and the clock one). Any suggestions on this front would be greatly appreciated? Thanks, Charles