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From: Ralf Baechle <ralf@linux-mips.org>
To: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] MIPS: perf: Fix I6400 event numbers
Date: Tue, 17 May 2016 14:52:38 +0200	[thread overview]
Message-ID: <20160517125238.GE14481@linux-mips.org> (raw)
In-Reply-To: <1463423555-5184-1-git-send-email-james.hogan@imgtec.com>

On Mon, May 16, 2016 at 07:32:35PM +0100, James Hogan wrote:

> Fix perf hardware performance counter event numbers for I6400. This core
> does not follow the performance event numbering scheme of previous MIPS
> cores. All performance counters (both odd and even) are capable of
> counting any of the available events.
> 
> Fixes: 4e88a8621301 ("MIPS: Add cases for CPU_I6400")

Thanks, applied.

  Ralf

      reply	other threads:[~2016-05-17 12:52 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-16 18:32 [PATCH] MIPS: perf: Fix I6400 event numbers James Hogan
2016-05-17 12:52 ` Ralf Baechle [this message]

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