From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752756AbcEQMw5 (ORCPT ); Tue, 17 May 2016 08:52:57 -0400 Received: from eddie.linux-mips.org ([148.251.95.138]:47278 "EHLO cvs.linux-mips.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751248AbcEQMw4 (ORCPT ); Tue, 17 May 2016 08:52:56 -0400 Date: Tue, 17 May 2016 14:52:38 +0200 From: Ralf Baechle To: James Hogan Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: perf: Fix I6400 event numbers Message-ID: <20160517125238.GE14481@linux-mips.org> References: <1463423555-5184-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1463423555-5184-1-git-send-email-james.hogan@imgtec.com> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 16, 2016 at 07:32:35PM +0100, James Hogan wrote: > Fix perf hardware performance counter event numbers for I6400. This core > does not follow the performance event numbering scheme of previous MIPS > cores. All performance counters (both odd and even) are capable of > counting any of the available events. > > Fixes: 4e88a8621301 ("MIPS: Add cases for CPU_I6400") Thanks, applied. Ralf