From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932256AbcEYFFt (ORCPT ); Wed, 25 May 2016 01:05:49 -0400 Received: from e33.co.us.ibm.com ([32.97.110.151]:54255 "EHLO e33.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754986AbcEYFFq (ORCPT ); Wed, 25 May 2016 01:05:46 -0400 X-IBM-Helo: d03dlp02.boulder.ibm.com X-IBM-MailFrom: ego@linux.vnet.ibm.com X-IBM-RcptTo: mpe@ellerman.id.au;linuxppc-dev@lists.ozlabs.org;mikey@neuling.org;paulus@ozlabs.org;linux-kernel@vger.kernel.org Date: Wed, 25 May 2016 10:35:36 +0530 From: Gautham R Shenoy To: "Shreyas B. Prabhu" Cc: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, paulus@ozlabs.org, linux-kernel@vger.kernel.org, mikey@neuling.org, ego@linux.vnet.ibm.com, maddy@linux.vnet.ibm.com Subject: Re: [PATCH v4 08/10] powerpc/powernv: Add platform support for stop instruction Message-ID: <20160525050536.GA16463@in.ibm.com> Reply-To: ego@linux.vnet.ibm.com References: <1464095714-48772-1-git-send-email-shreyas@linux.vnet.ibm.com> <1464095714-48772-9-git-send-email-shreyas@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1464095714-48772-9-git-send-email-shreyas@linux.vnet.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16052505-0009-0000-0000-000037AFDA3E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shreyas, On Tue, May 24, 2016 at 06:45:12PM +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. This instruction replaces > instructions like nap, sleep, rvwinkle. > b) new per thread SPR named Processor Stop Status and Control Register > (PSSCR) is added which controls the behavior of stop instruction. > > PSSCR layout: > ---------------------------------------------------------- > | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | > ---------------------------------------------------------- > 0 4 41 42 43 44 48 54 56 60 > > PSSCR key fields: > Bits 0:3 - Power-Saving Level Status. This field indicates the lowest > power-saving state the thread entered since stop instruction was last > executed. > > Bit 42 - Enable State Loss > 0 - No state is lost irrespective of other fields > 1 - Allows state loss > > Bits 44:47 - Power-Saving Level Limit > This limits the power-saving level that can be entered into. > > Bits 60:63 - Requested Level > Used to specify which power-saving level must be entered on executing > stop instruction > > This patch adds support for stop instruction and PSSCR handling. This version looks good to me. Reviewed-by: Gautham R. Shenoy -- Thanks and Regards gautham.