From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161862AbcE3Spg (ORCPT ); Mon, 30 May 2016 14:45:36 -0400 Received: from down.free-electrons.com ([37.187.137.238]:48323 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1161557AbcE3Spf (ORCPT ); Mon, 30 May 2016 14:45:35 -0400 Date: Mon, 30 May 2016 20:45:32 +0200 From: Maxime Ripard To: Vishnu Patekar Cc: linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, wens@csie.org, sboyd@codeaurora.org, emilio@elopez.com.ar, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] clk: sunxi: predivider handling for factors clock Message-ID: <20160530184532.GD4908@lukather> References: <1461084466-20889-1-git-send-email-vishnupatekar0510@gmail.com> <1461084466-20889-2-git-send-email-vishnupatekar0510@gmail.com> <20160502111337.GR17159@lukather> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="VUDLurXRWRKrGuMn" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --VUDLurXRWRKrGuMn Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Vishnu, On Mon, May 16, 2016 at 07:28:42AM +0800, Vishnu Patekar wrote: > > > @@ -307,7 +305,7 @@ static void sun6i_get_ahb1_factors(struct factors= _request *req) > > > div =3D DIV_ROUND_UP(req->parent_rate, req->rate); > > > > > > /* calculate pre-divider if parent is pll6 */ > > > - if (req->parent_index =3D=3D SUN6I_AHB1_PARENT_PLL6) { > > > + if (req->prediv_width) { > > > if (div < 4) > > > calcp =3D 0; > > > else if (div / 2 < 4) > > > > You should also remove that code from that function. Now that the core > > can tell the pre-divider configuration, it can adjust the parent rate > > so that you don't have to care anymore. > > We still need to get m factor when it's called from set_rate and > determine_rate. >=20 > Sorry, I did not your "that code from that function" meaning. I assumed > you're talking about m factor in sun6i_get_ahb1_factors. Sorry for the late answer. I don't know if you've seen it, but I have been working on a new clock framework. I went over all the A83T clocks, and most of them could be covered. The issue only lies in the PLLs and their additional 1-bit dividers. If we just choos to ignore (one of) them, it should be pretty trivial to implement with the current clock classes we have. There's also the current assumption that there's a single parent that has a pre-divider, but that can easily be fixed by setting up an array. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --VUDLurXRWRKrGuMn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXTIpMAAoJEBx+YmzsjxAghdoQAJ7Y/UbrtkajuDfvf6G/FSZh sS/SQMGVjoOJ4XkOfzpEhMI6EY53YTaVV7kYNkMdVx+vicjdwR+0DRMbt+poOebH f/bFel/lekquZ5jpudDY+kwmAqaSfU8mxdYLpQRTz1l4axcMfUBhKxzq/YjUnb1E kPMxsBnFbmwiyj4Z3bQIg0wzamq+tmDnzpjQTLqqyKi1+FY/mj9xsrgvr49xt6TW 2pUCl4drDc0QE97IxTrF1iTT/n6WFl/8Wa6UYF3UyPPGTpwlXwBAORvQxRpVO92Z olCrAdtRwjZeg4rCaBmqLVWb4q3oW88+4DCTI7ALvcF5AvOWCjoTs/B5rLOBmWl+ hnTUeHZQLXL9Jk5Pc+Cgx+7L92QMdN9GuzArZvtR4s7mb6Fkl29e+IYS6y9qtjRd gDrMCDO3tavBIKrQEdNgM840ZgHDGINB/9h+/cJGwFKQsjswayo4vgXr8klIGYiJ /eDQetqnrOy17UoGw4CudGyb7qawm984z2l14P+zGUbnGbPcUbqOc6YI5m99OL7f OODC3sY1dn0g+Xl8Fpr7fsnWLQNXkhHwoXVUh3YfWdiUEPd6JAC0z742DpVEUWa0 7dhvF1aMGfIoOEBCLZnMq6ukp6uqe5iegiWxwcELlRYH24woYY741RxoRUGssvuc h5GnoTIc8+YlVMGPIFci =l7wO -----END PGP SIGNATURE----- --VUDLurXRWRKrGuMn--