From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932642AbcFJO7C (ORCPT ); Fri, 10 Jun 2016 10:59:02 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:38903 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751899AbcFJO7A (ORCPT ); Fri, 10 Jun 2016 10:59:00 -0400 Date: Fri, 10 Jun 2016 15:59:15 +0100 From: Lee Jones To: Laxman Dewangan Cc: broonie@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V2 2/2] mfd: max77620: Mask/unmask interrupt before/after servicing it Message-ID: <20160610145915.GD7351@dell> References: <1465485187-9973-1-git-send-email-ldewangan@nvidia.com> <1465485187-9973-2-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1465485187-9973-2-git-send-email-ldewangan@nvidia.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 09 Jun 2016, Laxman Dewangan wrote: > The programming guidelines of the MAX77620 for servicing interrupt is: > 1. When interrupt occurs from PMIC, mask the PMIC interrupt by > setting GLBLM. > 2. Read IRQTOP and service the interrupt. > 3. Once all interrupts has been checked and serviced, the interrupt > service routine un-masks the hardware interrupt line by clearing > GLBLM. > > Add the pre and post interrupt service handler for mask and unmask the > global interrupt mask bit (for step 1 and 3) as callback from regmap-irq. > > Signed-off-by: Laxman Dewangan > > --- > Changes from V1: > - Rename pre/post handler to max77620_irq_{mask/unmask} > - Change commit description to say mask/unamsk clearly. > > drivers/mfd/max77620.c | 55 +++++++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 46 insertions(+), 9 deletions(-) Applied, thanks. > diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c > index f32fbb8..6005fe2 100644 > --- a/drivers/mfd/max77620.c > +++ b/drivers/mfd/max77620.c > @@ -111,15 +111,6 @@ static const struct mfd_cell max20024_children[] = { > }, > }; > > -static struct regmap_irq_chip max77620_top_irq_chip = { > - .name = "max77620-top", > - .irqs = max77620_top_irqs, > - .num_irqs = ARRAY_SIZE(max77620_top_irqs), > - .num_regs = 2, > - .status_base = MAX77620_REG_IRQTOP, > - .mask_base = MAX77620_REG_IRQTOPM, > -}; > - > static const struct regmap_range max77620_readable_ranges[] = { > regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), > }; > @@ -180,6 +171,51 @@ static const struct regmap_config max20024_regmap_config = { > .volatile_table = &max77620_volatile_table, > }; > > +/* > + * MAX77620 and MAX20024 has the following steps of the interrupt handling > + * for TOP interrupts: > + * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM. > + * 2. Read IRQTOP and service the interrupt. > + * 3. Once all interrupts has been checked and serviced, the interrupt service > + * routine un-masks the hardware interrupt line by clearing GLBLM. > + */ > +static int max77620_irq_global_mask(void *irq_drv_data) > +{ > + struct max77620_chip *chip = irq_drv_data; > + int ret; > + > + ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, > + MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK); > + if (ret < 0) > + dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret); > + > + return ret; > +} > + > +static int max77620_irq_global_unmask(void *irq_drv_data) > +{ > + struct max77620_chip *chip = irq_drv_data; > + int ret; > + > + ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, > + MAX77620_GLBLM_MASK, 0); > + if (ret < 0) > + dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret); > + > + return ret; > +} > + > +static struct regmap_irq_chip max77620_top_irq_chip = { > + .name = "max77620-top", > + .irqs = max77620_top_irqs, > + .num_irqs = ARRAY_SIZE(max77620_top_irqs), > + .num_regs = 2, > + .status_base = MAX77620_REG_IRQTOP, > + .mask_base = MAX77620_REG_IRQTOPM, > + .handle_pre_irq = max77620_irq_global_mask, > + .handle_post_irq = max77620_irq_global_unmask, > +}; > + > /* max77620_get_fps_period_reg_value: Get FPS bit field value from > * requested periods. > * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560 > @@ -433,6 +469,7 @@ static int max77620_probe(struct i2c_client *client, > if (ret < 0) > return ret; > > + max77620_top_irq_chip.irq_drv_data = chip; > ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, > IRQF_ONESHOT | IRQF_SHARED, > chip->irq_base, &max77620_top_irq_chip, -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog