From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753517AbcFLLoh (ORCPT ); Sun, 12 Jun 2016 07:44:37 -0400 Received: from mail.kernel.org ([198.145.29.136]:52472 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752702AbcFLLog (ORCPT ); Sun, 12 Jun 2016 07:44:36 -0400 Date: Sun, 12 Jun 2016 19:43:53 +0800 From: Shawn Guo To: Dong Aisheng Cc: linux-clk@vger.kernel.org, anson.huang@nxp.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents Message-ID: <20160612114353.GE20243@tiger> References: <1465396420-27064-1-git-send-email-aisheng.dong@nxp.com> <1465396420-27064-7-git-send-email-aisheng.dong@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1465396420-27064-7-git-send-email-aisheng.dong@nxp.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote: > pllx_bypass_src mux shouldn't be the parent of pllx clock > since it's only valid when when pllx BYPASS bit is set. > Thus it is actually one parent of pllx_bypass only. > > Instead, pllx parent should be fixed to osc according to > reference manual. > Other plls have the same issue. > > e.g. before fix, the pll tree is: > osc 6 6 24000000 0 0 > pll1_bypass_src 0 0 24000000 0 0 > pll1 0 0 792000000 0 0 > pll1_bypass 0 0 792000000 0 0 > pll1_sys 0 0 792000000 0 0 > > After the fix, it's: > osc 6 6 24000000 0 0 > pll1 0 0 792000000 0 0 > pll1_bypass 0 0 792000000 0 0 > pll1_sys 0 0 792000000 0 0 > > Signed-off-by: Dong Aisheng I squashed 7 ~ 11 into one patch and applied it, thanks. Shawn