Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents

Shawn Guo
2016-06-12T11:44:37Z

On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> pllx_bypass_src mux shouldn't be the parent of pllx clock
> since it's only valid when when pllx BYPASS bit is set.
> Thus it is actually one parent of pllx_bypass only.
>
> Instead, pllx parent should be fixed to osc according to
> reference manual.
> Other plls have the same issue.
>
> e.g. before fix, the pll tree is:
> osc 6 6 24000000 0 0
> pll1_bypass_src 0 0 24000000 0 0
> pll1 0 0 792000000 0 0
> pll1_bypass 0 0 792000000 0 0
> pll1_sys 0 0 792000000 0 0
>
> After the fix, it's:
> osc 6 6 24000000 0 0
> pll1 0 0 792000000 0 0
> pll1_bypass 0 0 792000000 0 0
> pll1_sys 0 0 792000000 0 0
>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

I squashed 7 ~ 11 into one patch and applied it, thanks.

Shawn