From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752198AbcFUPsR (ORCPT ); Tue, 21 Jun 2016 11:48:17 -0400 Received: from mga04.intel.com ([192.55.52.120]:19276 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752105AbcFUPsO (ORCPT ); Tue, 21 Jun 2016 11:48:14 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,504,1459839600"; d="scan'208";a="1006757345" Date: Tue, 21 Jun 2016 21:25:02 +0530 From: Vinod Koul To: Kedareswara rao Appana Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, dan.j.williams@intel.com, appanad@xilinx.com, moritz.fischer@ettus.com, laurent.pinchart@ideasonboard.com, luis@debethencourt.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: Re: [PATCH 2/4] dmaengine: vdma: Add support for mulit-channel dma mode Message-ID: <20160621155502.GB16910@localhost> References: <1465549954-30220-1-git-send-email-appanad@xilinx.com> <1465549954-30220-3-git-send-email-appanad@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1465549954-30220-3-git-send-email-appanad@xilinx.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 10, 2016 at 02:42:32PM +0530, Kedareswara rao Appana wrote: > This patch adds support for AXI DMA multi-channel dma mode > Multichannel mode enables DMA to connect to multiple masters > And slaves on the streaming side. > In Multichannel mode AXI DMA supports 2D transfers. Funny formatting! Can you elobrate what you meant by Multichannel mode? This patch seems to do two things, one is to add interleaved dma support and something else. Can you explain the latter part? > /** > + * struct xilinx_mcdma_config - DMA Multi channel configuration structure > + * @tdest: Channel to operate on > + * @tid: Channel configuration > + * @tuser: Tuser configuration > + * @ax_user: ax_user value > + * @ax_cache: ax_cache value > + */ > +struct xilinx_mcdma_config { > + u8 tdest; > + u8 tid; > + u8 tuser; > + u8 ax_user; > + u8 ax_cache; can you describe these in details, what do these do, what are the values to be programmed? -- ~Vinod