Re: [PATCH] cacheinfo: Introduce cache id

["Luck, Tony" <tony.luck@intel.com>]

> Basically all cache indices carry the APIC ID of the core, so L1D on
> CPU0 has ID 0 and then L1I has ID 0 too and then L2 has also the same
> ID.
> 
> How does that look on a CAT system? Do all the different cache levels
> get different IDs?

For CAT we only need the IDs to be unique at each level. Our tentative
syntax for the schema file for CAT looks like this (for a theoretical
system supporting CAT in both L2 and L3 with two L3 caches and eight L2 caches)

L3:id0=fff;id1=ff0
L2:id0=3;id1=c;id2=30;id3=c0;id4=3;id5=c;id6=30;id7=c0

We wondered about using cpu numbers (i.e. when we say id0 on the "L3"
line we mean the L3 cache that is used by cpu0 (and a bunch of other
cpus) and on the L2 line it means the L2 cache shared by cpu0 (and its
hyperthread core buddy).  But that gets weird with hot plug. cpu0 may
be offline, but the caches it shares still exist.

-Tony