From: Ingo Molnar <mingo@kernel.org>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: "Yu, Fenghua" <fenghua.yu@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
"Anvin, H Peter" <h.peter.anvin@intel.com>,
Ingo Molnar <mingo@elte.hu>, Borislav Petkov <bp@suse.de>,
Stephane Eranian <eranian@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v2 2/3] Documentation, ABI: Add a document entry for cache id
Date: Fri, 8 Jul 2016 20:07:46 +0200 [thread overview]
Message-ID: <20160708180746.GB4429@gmail.com> (raw)
In-Reply-To: <3908561D78D1C84285E8C5FCA982C28F3A15599C@ORSMSX114.amr.corp.intel.com>
* Luck, Tony <tony.luck@intel.com> wrote:
> > It means one cache's id is unique in all caches with same cache index number.
> > For example, in all caches with index3 (i.e. level3), cache id 0 is unique to identify
> > a L3 cache. But in caches with index 0 (i.e. Level0), there is also a cache id 0.
> > So cache id is unique in one index. But not unique in two different index.
>
> > Does that make sense? I hope I express that correctly.
>
> We use "index" rather than "level" because that is the terminology used
> in /sys/devices/system/cpu/cpu*/cache/index*
Who can we ... thank for that nonsensical naming? :-/
> E.g. on most Intel cpus you'll typically find "index0" is the L1-data cache,
> "index1" is the L1-instruction cache, "index3" is the L2-unified cache and
> "index4" is the L3-unified cache.
Crazy. What was wrong with using 'level' or 'depth'?
Thanks,
Ingo
next prev parent reply other threads:[~2016-07-08 18:07 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-06 22:07 [PATCH v2 0/3] Cache id Fenghua Yu
2016-07-06 22:07 ` [PATCH v2 1/3] cacheinfo: Introduce cache id Fenghua Yu
2016-07-06 22:07 ` [PATCH v2 2/3] Documentation, ABI: Add a document entry for " Fenghua Yu
2016-07-08 8:41 ` Ingo Molnar
2016-07-08 17:06 ` Yu, Fenghua
2016-07-08 17:29 ` Luck, Tony
2016-07-08 18:07 ` Ingo Molnar [this message]
2016-07-08 18:41 ` Borislav Petkov
2016-07-08 18:47 ` Luck, Tony
2016-07-08 18:55 ` Borislav Petkov
2016-07-08 19:34 ` Ingo Molnar
2016-07-09 8:17 ` Borislav Petkov
2016-07-08 18:06 ` Ingo Molnar
2016-07-06 22:07 ` [PATCH v2 3/3] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-07-07 16:21 ` [PATCH v2 0/3] Cache id Borislav Petkov
2016-07-08 3:13 ` Yu, Fenghua
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