From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755946AbcGHSH5 (ORCPT ); Fri, 8 Jul 2016 14:07:57 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:38777 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755815AbcGHSHu (ORCPT ); Fri, 8 Jul 2016 14:07:50 -0400 Date: Fri, 8 Jul 2016 20:07:46 +0200 From: Ingo Molnar To: "Luck, Tony" Cc: "Yu, Fenghua" , Thomas Gleixner , "Anvin, H Peter" , Ingo Molnar , Borislav Petkov , Stephane Eranian , Peter Zijlstra , Vikas Shivappa , "Shankar, Ravi V" , linux-kernel , x86 Subject: Re: [PATCH v2 2/3] Documentation, ABI: Add a document entry for cache id Message-ID: <20160708180746.GB4429@gmail.com> References: <1467842838-57246-1-git-send-email-fenghua.yu@intel.com> <1467842838-57246-3-git-send-email-fenghua.yu@intel.com> <20160708084146.GA4508@gmail.com> <3E5A0FA7E9CA944F9D5414FEC6C712205DFD3208@ORSMSX106.amr.corp.intel.com> <3908561D78D1C84285E8C5FCA982C28F3A15599C@ORSMSX114.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3908561D78D1C84285E8C5FCA982C28F3A15599C@ORSMSX114.amr.corp.intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Luck, Tony wrote: > > It means one cache's id is unique in all caches with same cache index number. > > For example, in all caches with index3 (i.e. level3), cache id 0 is unique to identify > > a L3 cache. But in caches with index 0 (i.e. Level0), there is also a cache id 0. > > So cache id is unique in one index. But not unique in two different index. > > > Does that make sense? I hope I express that correctly. > > We use "index" rather than "level" because that is the terminology used > in /sys/devices/system/cpu/cpu*/cache/index* Who can we ... thank for that nonsensical naming? :-/ > E.g. on most Intel cpus you'll typically find "index0" is the L1-data cache, > "index1" is the L1-instruction cache, "index3" is the L2-unified cache and > "index4" is the L3-unified cache. Crazy. What was wrong with using 'level' or 'depth'? Thanks, Ingo