Re: [PATCH 05/32] x86/intel_rdt: Implement scheduling support for Intel RDT

["Luck, Tony" <tony.luck@intel.com>]

On Mon, Jul 25, 2016 at 11:31:24AM -0500, Nilay Vaish wrote:
> I was thinking more about this software caching of CLOSids.  How
> likely do you think these CLOSids would be found cached?  I think the
> software cache would be very infrequently accessed, so it seems you
> are likely to miss these in all levels of cache hierarchy and more
> likely to have to fetch these from the main memory, which itself might
> cost ~250 cycles.

We need to avoid reading the PQR_ASSOC MSR (which would cost far
more than 250 cycles).  Life is complicated here because this
MSR contains the CLOSID in the upper half, and the RMID (owned
by the perf code to measure cache occupancy and memory bandwidth)
in the lower half.

I've wondered whether it would be possible to include both the
CLOSID and the RMID in either the task or thread struct (in some
spot that was likely to be pulled into cache by access to adjacent
members during context switch).  This would smooth the path in
context switch (since we can look at the values from the previous
process and compare them to the ones for the new process to see
whether we need to do the wrmsr()).  But it likely needs a bunch
of other changes to update the values when a process migrates
between cpus to get the closid precedence that tglx requires.

-Tony