Re: [PATCH 4/9] clk: sunxi-ng: mux: Add support for mux tables

Chen-Yu Tsai
2016-07-27T07:30:47Z

On Wed, Jul 27, 2016 at 3:18 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> On Wed, 27 Jul 2016 08:59:34 +0200
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
>
>> On Tue, Jul 26, 2016 at 07:43:06PM +0200, Jean-Francois Moine wrote:
>> > On Tue, 26 Jul 2016 15:04:26 +0800
>> > Chen-Yu Tsai <wens@csie.org> wrote:
>> >
>> > > Some clock muxes have holes, i.e. invalid or unconnected inputs,
>> > > between parent mux values.
>> > >
>> > > Add support for specifying a mux table to map clock parents to
>> > > mux values.
>> >
>> > Putting empty strings in the holes should work. No?
>> > Ex:
>> >
>> > static const char * const csi_mclk_parents[] =
>> > { "pll-video0", "pll-video1", "", "", "", "osc24M" };
>>
>> Not really. The clock would be declared as orphan, while it's really
>> not.
>>
>> Parenting functions would also not work as expected,
>> clk_hw_get_parent_by_index being the obvious example, in that case
>> returning the empty string for an invalid parent, while it should
>> really return NULL.
>
> I don't see why the clock should be orphan.
> Then, when a parent is "", clk_hw_get_parent_by_index() returns NULL.

There's no requirement for parent clk indexes to match the actual
register value, is there?

ChenYu