From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758551AbcG1OCx (ORCPT ); Thu, 28 Jul 2016 10:02:53 -0400 Received: from foss.arm.com ([217.140.101.70]:49117 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758497AbcG1OCp (ORCPT ); Thu, 28 Jul 2016 10:02:45 -0400 Date: Thu, 28 Jul 2016 15:02:37 +0100 From: Mark Rutland To: Rich Felker Cc: linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, devicetree@vger.kernel.org, Jason Cooper , Marc Zyngier , Rob Herring , Thomas Gleixner Subject: Re: [PATCH v4 2/2] irqchip: add J-Core AIC driver Message-ID: <20160728140236.GC5881@leverpostej> References: <862a5642f4a30f062171bbc14fe95a729eab8ba2.1469595861.git.dalias@libc.org> <20160727101235.GC12880@leverpostej> <20160727130606.GA15995@brightrain.aerifal.cx> <20160727132252.GB17195@leverpostej> <20160727170709.GC15995@brightrain.aerifal.cx> <20160727173152.GH17195@leverpostej> <20160727230124.GE15995@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160727230124.GE15995@brightrain.aerifal.cx> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 27, 2016 at 07:01:24PM -0400, Rich Felker wrote: > On Wed, Jul 27, 2016 at 06:31:52PM +0100, Mark Rutland wrote: > > IIUC, that means you *could* implement per-irq masking by having the > > CPU's mask value set to 0, and flipping the priority of an IRQ between 0 > > and 1 to disable/enable. > > > > Though from your prior comments it sounds like for AIC2 writes to the > > MMIO priority registers are ignored, so that would not work for AIC2? > > Right. The register with 8 4-bit fields only made sense for the setup > with 8 irq lines with variable priority; the aic2 has 64 lines with > static priorities. Thinking about this a little further, this is a good argument for the "jcore,aic1" *not* being a valid fallback entry in an AIC2 compatible list. Anything wanting to rely on this behaviour of AIC1 would be broken on AIC2. That being the case, no DT should have "jcore,aic1" for an AIC2 node, and we can explciitly check for the AIC1 string for AIC1-specific initialisation code (though regardless, it's worht a comment). A further curiosity: what static priority values for AIC2 apply to interrupts? Does it apply 0xf (or some over value) uniformly, or can AIC2 interrupts potentially have varied priorities? Thanks, Mark.