From: Matt Roper <matthew.d.roper@intel.com>
To: Lyude <cpaul@redhat.com>
Cc: intel-gfx@lists.freedesktop.org,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"David Airlie" <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
"Daniel Vetter" <daniel.vetter@intel.com>
Subject: Re: [Intel-gfx] [PATCH v4 0/6] Finally fix watermarks
Date: Thu, 28 Jul 2016 17:03:52 -0700 [thread overview]
Message-ID: <20160729000352.GR32025@intel.com> (raw)
In-Reply-To: <1469554483-24999-1-git-send-email-cpaul@redhat.com>
This is completely untested (and probably horribly broken/buggy), but
here's a quick mockup of the general approach I was thinking for
ensuring DDB & WM's can be updated together while ensuring the
three-step pipe flushing process is honored:
https://github.com/mattrope/kernel/commits/experimental/lyude_ddb
Basically the idea is to take note of what's happening to the pipe's DDB
allocation (shrinking, growing, unchanged, etc.) during the atomic check
phase; then during the commit phase, we loop over the CRTC's three times
instead of just once, but only operate on a subset of the CRTC's in each
loop. While operating on each CRTC, the plane, WM, and DDB all get
programmed together and have a single flush for all three.
Matt
On Tue, Jul 26, 2016 at 01:34:36PM -0400, Lyude wrote:
> Latest version of https://lkml.org/lkml/2016/7/26/290 . Resending the whole
> thing to keep it in one place.
>
> Lyude (5):
> drm/i915/skl: Add support for the SAGV, fix underrun hangs
> drm/i915/skl: Only flush pipes when we change the ddb allocation
> drm/i915/skl: Fix extra whitespace in skl_flush_wm_values()
> drm/i915/skl: Update plane watermarks atomically during plane updates
> drm/i915/skl: Always wait for pipes to update after a flush
>
> Matt Roper (1):
> drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
>
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_display.c | 24 ++++
> drivers/gpu/drm/i915/intel_drv.h | 4 +
> drivers/gpu/drm/i915/intel_pm.c | 240 +++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_sprite.c | 2 +
> 6 files changed, 255 insertions(+), 23 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
next prev parent reply other threads:[~2016-07-29 0:03 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-26 17:34 [PATCH v4 0/6] Finally fix watermarks Lyude
2016-07-26 17:34 ` [PATCH v4 1/6] drm/i915/skl: Add support for the SAGV, fix underrun hangs Lyude
2016-07-28 13:13 ` Matt Roper
2016-08-02 11:16 ` [v4,1/6] " Hans de Goede
2016-07-26 17:34 ` [PATCH v4 2/6] drm/i915/gen9: Only copy WM results for changed pipes to skl_hw Lyude
2016-07-26 17:34 ` [PATCH v4 3/6] drm/i915/skl: Only flush pipes when we change the ddb allocation Lyude
2016-07-28 13:14 ` Matt Roper
2016-07-26 17:34 ` [PATCH v4 4/6] drm/i915/skl: Fix extra whitespace in skl_flush_wm_values() Lyude
2016-07-26 17:34 ` [PATCH v4 5/6] drm/i915/skl: Update plane watermarks atomically during plane updates Lyude
2016-07-28 13:15 ` Matt Roper
2016-07-26 17:34 ` [PATCH v4 6/6] drm/i915/skl: Always wait for pipes to update after a flush Lyude
2016-07-29 0:03 ` Matt Roper [this message]
2016-07-29 9:39 ` [Intel-gfx] [PATCH v4 0/6] Finally fix watermarks Ville Syrjälä
2016-07-29 18:48 ` Lyude
2016-07-29 19:26 ` Ville Syrjälä
2016-07-29 19:46 ` Lyude
2016-07-29 20:41 ` Matt Roper
2016-08-01 11:50 ` Ville Syrjälä
2016-07-29 20:33 ` Matt Roper
2016-08-01 8:48 ` Maarten Lankhorst
2016-08-01 11:48 ` Ville Syrjälä
2016-08-02 15:41 ` Maarten Lankhorst
2016-08-02 15:59 ` Ville Syrjälä
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