[PATCH v4 6/6] drm/i915/skl: Always wait for pipes to update after a flush

Lyude
2016-07-26T17:35:05Z

Unfortunately right now we don't really update watermarks on Skylake
properly, since ideally we'd be updating both the ddb allocations, plane
properties, and watermarks all in a single go. Until this is fixed
however, we can improve things somewhat by adding a vblank wait after
the third iteration of pipe flushes, since this forces us to always wait
for new ddb allocations to take affect before trying to change them
again.

Signed-off-by: Lyude <cpaul@redhat.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d469ad2..a26dbd9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3973,8 +3973,11 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
/*
* Third pass: flush the pipes that got more space allocated.
*
- * We don't need to actively wait for the update here, next vblank
- * will just get more DDB space with the correct WM values.
+ * While the hardware doesn't require to wait for the next vblank here,
+ * continuing before the pipe finishes updating could result in us
+ * trying to update the wm values again before the pipe finishes
+ * updating, which results in the hardware using intermediate wm values
+ * and subsequently underrunning pipes.
*/
for_each_intel_crtc(dev, crtc) {
if (!crtc->active)
@@ -3990,6 +3993,16 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
continue;

skl_wm_flush_pipe(dev_priv, pipe, 3);
+
+ /*
+ * The only time we can get away with not waiting for an update
+ * is when we just enabled the pipe, e.g. when it doesn't have
+ * vblanks enabled anyway.
+ */
+ if (drm_crtc_vblank_get(&crtc->base) == 0) {
+ intel_wait_for_vblank(dev, pipe);
+ drm_crtc_vblank_put(&crtc->base);
+ }
}
}

--
2.7.4