From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752560AbcHIDc0 (ORCPT ); Mon, 8 Aug 2016 23:32:26 -0400 Received: from mail.skyhub.de ([78.46.96.112]:35724 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752499AbcHIDcW (ORCPT ); Mon, 8 Aug 2016 23:32:22 -0400 Date: Tue, 9 Aug 2016 05:32:04 +0200 From: Borislav Petkov To: york sun Cc: "linux-edac@vger.kernel.org" , "morbidrsa@gmail.com" , "oss@buserror.net" , Stuart Yoder , Doug Thompson , "mchehab@kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1 Message-ID: <20160809033204.GA11445@nazgul.tnic> References: <1470351518-22404-1-git-send-email-york.sun@nxp.com> <1470351518-22404-4-git-send-email-york.sun@nxp.com> <20160808071111.GB20800@nazgul.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 08, 2016 at 03:39:44PM +0000, york sun wrote: > RFXE is cleared by default. So for most SoCs, this is not even a concern > at all. But for e500v1, when RIO or PCI are used, this bit is set > specifically to catch an error by machine check (see commit 4e0e3435). > This is not the uncorrectable error from DDR. We will be better off to > let this error happen. So I'm reading this: "With this bit set, EDAC driver can't get the interrupt in case of uncorrectable error. So this bit is cleared in favor of EDAC." AFAIU, it means, RFXE bit remains clear so EDAC will get the interrupt for the uncorrectable error (UE). So on those !e500v1 systems, EDAC be handling those UEs. Am I close? If so, can EDAC handle the UE? -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --