From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932509AbcHISt6 (ORCPT ); Tue, 9 Aug 2016 14:49:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40268 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932207AbcHISt5 (ORCPT ); Tue, 9 Aug 2016 14:49:57 -0400 Date: Tue, 9 Aug 2016 20:49:44 +0200 From: Oleg Nesterov To: Pratyush Anand Cc: linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, wcohen@redhat.com, dave.long@linaro.org, steve.capper@linaro.org, srikar@linux.vnet.ibm.com, vijaya.kumar@caviumnetworks.com, Shi Yang , Andre Przywara , Ard Biesheuvel , Ashok Kumar , James Morse , Jungseok Lee , "Kirill A. Shutemov" , Mark Rutland , Masami Hiramatsu , Robin Murphy , Sandeepa Prabhu , Shaokun Zhang , "Suzuki K. Poulose" , Vladimir Murzin Subject: Re: [PATCH 5/5] arm64: Add uprobe support Message-ID: <20160809184943.GA17112@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 09 Aug 2016 18:49:56 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/02, Pratyush Anand wrote: > > This patch adds support for uprobe on ARM64 architecture. I know nothing about ARM, so I can't actually review this change. But it looks good to me ;) Just one note, > +int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) > +{ > + struct uprobe_task *utask = current->utask; > + > + /* saved fault code is restored in post_xol */ > + utask->autask.saved_fault_code = current->thread.fault_code; > + > + /* An invalid fault code between pre/post xol event */ > + current->thread.fault_code = UPROBE_INV_FAULT_CODE; > + > + /* Instruction point to execute ol */ > + instruction_pointer_set(regs, utask->xol_vaddr); > + > + user_enable_single_step(current); I don't think we want user_{enable,disable{_single_step in the long term, please look at 9bd1190a11c9d2 "uprobes/x86: Do not (ab)use TIF_SINGLESTEP /user_*_single_step() for single-stepping". it seems that ARM64 sets/clears TIF_SINGLESTEP. You can also lool at saved_tf logic, probably ARM64 needs the same. However, I agree we can do this later and initial version can use these ptrace helpers. Oleg.