From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933834AbcHJUt5 (ORCPT ); Wed, 10 Aug 2016 16:49:57 -0400 Received: from foss.arm.com ([217.140.101.70]:49160 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933080AbcHJSLm (ORCPT ); Wed, 10 Aug 2016 14:11:42 -0400 Date: Wed, 10 Aug 2016 16:43:24 +0100 From: Juri Lelli To: Sudeep Holla Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, peterz@infradead.org, vincent.guittot@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@arm.linux.org.uk, lorenzo.pieralisi@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, morten.rasmussen@arm.com, dietmar.eggemann@arm.com, broonie@kernel.org, Liviu Dudau , Pawel Moll , Ian Campbell , Kumar Gala Subject: Re: [PATCH v6 3/8] arm, dts: add TC2 cpu capacity-dmips-mhz information Message-ID: <20160810154324.GJ3540@e106622-lin> References: <1468932048-31635-1-git-send-email-juri.lelli@arm.com> <1468932048-31635-4-git-send-email-juri.lelli@arm.com> <7ac935dc-9f8b-8af0-e67b-ef1c469d76f1@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7ac935dc-9f8b-8af0-e67b-ef1c469d76f1@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 10/08/16 16:33, Sudeep Holla wrote: > Hi Juri, > > On 19/07/16 13:40, Juri Lelli wrote: > >Add TC2 cpu capacity binding information. > > > > If you repost it, > > s/binding// > Yes, I think I'll need to repost, squashing the arm64 fix in the appropriate patch. Thanks. > >Cc: Liviu Dudau > >Cc: Sudeep Holla > > Acked-by: Sudeep Holla Thanks! > (assuming you take it via some other tree, let us know if it's > OK to merge the DTS separately and you want us to pick them) > As per off-line discussion with Russell, binding doc and arm bits should go via his patch system. While arm64 bits could go separately via aarch64. Does this make sense? Best, - Juri